1 comment:
File src/soc/intel/tigerlake/early_tcss.c:
void early_tcss_enable(void)
{
uint8_t dp_mode;
unsigned int num_ports;
int ret, i;
bool ufp, acc;
ret = google_chromeec_get_num_pd_ports(&num_ports);
if (ret < 0) {
printk(BIOS_ERR, "get_num_pd_ports failed unable to continue\n");
return;
}
for (i = 0; i < num_ports; i++) {
uint8_t port_map, mux_flags;
struct tcss_mux mux_data;
ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags);
if (ret < 0) {
printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", i);
continue;
}
ret = google_chromeec_pd_get_port_info(i, &port_map);
if (ret < 0) {
printk(BIOS_ERR, "port C%d: get_port_info failed\n", i);
continue;
}
mux_data.usb2_port = port_map & USB_2_PORT_MASK;
mux_data.usb3_port = (port_map & USB_3_PORT_MASK) >> 4;
//Add check for connected maybe?
ret = google_chromeec_usb_pd_control(i, &ufp, &acc, &dp_mode);
if (ret < 0) {
printk(BIOS_ERR, "port C%d: pd_control failed\n", i);
continue;
}
mux_data.usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED);
mux_data.dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED);
mux_data.cable = !!(mux_flags & USB_PD_CTRL_ACTIVE_CABLE);
mux_data.polarity = !!(mux_flags & USB_PD_MUX_POLARITY_INVERTED);
mux_data.hpd_irq = !!(mux_flags & USB_PD_MUX_HPD_IRQ);
mux_data.hpd_lvl = !!(mux_flags & USB_PD_MUX_HPD_LVL);
mux_data.ufp = !!ufp;
mux_data.acc = !!acc;
mux_data.dp_mode = dp_mode;
printk(BIOS_DEBUG, "Port %d mux=0x%x\n"
"USB2 port = %x\n"
"USB3 port = %x\n"
"DP Mode = %x\n"
"dp = %d\n"
"usb = %d\n"
"cable = %d\n"
"polarity = %d\n"
"hpd_lvl = %d\n"
"hpd_irq = %d\n"
"ufp = %d\n"
"dbg_acc = %d\n",
i, (unsigned int)mux_flags, mux_data.usb2_port,
mux_data.usb3_port, mux_data.dp_mode, mux_data.dp,
mux_data.usb, mux_data.cable, mux_data.polarity,
mux_data.hpd_lvl, mux_data.hpd_irq, mux_data.ufp,
mux_data.acc);
update_tcss_mux(i, mux_data);
}
}
Ok I guess I understand your view I just find it weird to move to mainboard since this will be appli […]
We do already have `mainboard_silicon_init_params()` in fsp_params.c for example, which calls into the mainboard to update UPDs. We also can't just assume that necessarily every Tiger Lake board will have the Chrome EC.
I have also been thinking about some re-organization with code that we want to probably share among Chrome OS boards, but not have it live in vendorcode/google/chromeos either (maybe someone wants to run an alternative OS on a chromebook, but they would still need this functionality)... so I hear your point of view as well, and I'm thinking about it, but for now, the mainboard is probably the simplest way.
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