Patch set 15:Code-Review +1
16 comments:
File src/mainboard/protectli/vault_bsw/acpi/superio.asl:
Patch Set #15, Line 13: Method (_STA, 0, NotSerialized) {
Should '{' be placed on newline?
File src/mainboard/protectli/vault_bsw/acpi_tables.c:
Patch Set #15, Line 12: #include <arch/smp/mpspec.h>
Are al these include files required?
File src/mainboard/protectli/vault_bsw/cmos.layout:
Patch Set #15, Line 60: 388 4 h 0 reboot_counter
Compare with FB FBG1701:
Is reboot_counter used?
Otherwise add
# reboot_counter reserved for core, not used by platform.
Patch Set #15, Line 70: 400 1 e 2 hyper_threading
unused
Patch Set #15, Line 80: 416 128 r 0 vbnv
ChromeOS and SandyBridge MRC not used!
File src/mainboard/protectli/vault_bsw/devicetree.cb:
Patch Set #15, Line 12: register "PcdIgdDvmt50PreAlloc" = "1"
Might use IDG_MEMSIZE_32MB
Patch Set #15, Line 77: # Disable use of ACPI mode
Comment what is done.
Use #Enable devices in PCI mode
Patch Set #15, Line 125: device pci 1f.0 on # 8086 229c - LPC bridge
TAB missing for alignment
File src/mainboard/protectli/vault_bsw/dsdt.asl:
Patch Set #15, Line 13: 0x02, // DSDT revision: ACPI v2.0 and up
One line comment use '/*'
Patch Set #15, Line 19: #include "onboard.h"
Is onboard.h required here?
File src/mainboard/protectli/vault_bsw/fadt.c:
Patch Set #15, Line 23: header->asl_compiler_revision = 1;
special reason not using = asl_revision?
File src/mainboard/protectli/vault_bsw/gpio.c:
Patch Set #15, Line 10: #include <soc/gpio.h>
Is soc/gpio.h the only required include file?
Remove empty line
File src/mainboard/protectli/vault_bsw/ramstage.c:
Patch Set #15, Line 10: #include <boardid.h>
Is boardid.h required?
File src/mainboard/protectli/vault_bsw/romstage.c:
Patch Set #15, Line 10: #include <fsp/car.h>
Is this car.h required?
Patch Set #15, Line 23: ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
ite_enable_serial() is done in early stage. Required to re-enable again?
(FSP only enables internal UART as COM1)
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