Attention is currently required from: Jason Glenesk, Raul Rangel.

Felix Held uploaded patch set #2 to this change.

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soc/amd/cezanne/fch: add ACPI I/O port setup

The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from
the reference code, but not the PPR. I've submitted a change request for
the PPR, so this mismatch might go away in the future. The case for
HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends
up being identical to the function in soc/amd/picasso, I'll move it to
the common AMD SoC code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f
---
M src/soc/amd/cezanne/fch.c
M src/soc/amd/cezanne/include/soc/iomap.h
M src/soc/amd/cezanne/include/soc/southbridge.h
3 files changed, 69 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/50270/2

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