Lijian Zhao has uploaded this change for review.

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google/sarien: Increase BIOS region to 28MB

Platform have a 32MB SPI chip, so we can increase the bios region from
16MB to 28MB.

BUG=b:119267832
TEST=Build and boot fine on sarien platform.

Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
---
M src/mainboard/google/sarien/chromeos.fmd
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29945/1

diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd
index 6631769..ec08b83 100644
--- a/src/mainboard/google/sarien/chromeos.fmd
+++ b/src/mainboard/google/sarien/chromeos.fmd
@@ -1,11 +1,11 @@
 FLASH@0xfe000000 0x2000000 {
-	SI_ALL@0x0 0x1000000 {
+	SI_ALL@0x0 0x400000 {
 		SI_DESC@0x0 0x1000
 		SI_EC@0x1000 0x100000
 		SI_GBE@0x101000 0x2000
-		SI_ME@0x103000 0xefd000
+		SI_ME@0x103000 0x2fd000
 	}
-	SI_BIOS@0x1000000 0x1000000 {
+	SI_BIOS@0x400000 0x1c00000 {
 		RW_SECTION_A@0x0 0x280000 {
 			VBLOCK_A@0x0 0x10000
 			FW_MAIN_A(CBFS)@0x10000 0x26ffc0
@@ -30,7 +30,7 @@
 			RW_NVRAM@0x2a000 0x6000
 		}
 		CONSOLE@0x530000 0x20000
-		RW_LEGACY(CBFS)@0x550000 0x6b0000
+		RW_LEGACY(CBFS)@0x550000 0x12b0000
 		WP_RO@0xc00000 0x400000 {
 			RO_VPD@0x0 0x4000
 			RO_UNUSED@0x4000 0xc000

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