3 comments:
File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
Patch Set #13, Line 18: # GPE configuration
I think you answered your own question?
Yes, I suppose :)
Skylake laptops seem to use the same GPIO communities. These are correct.
Patch Set #13, Line 150: # register "PcieRpEnable[6]" = "1"
I enabled it in the list of PCI devices and it probably doesn't hurt to enable it in general. […]
Port 7 actually backs SATA. Port 8 is NGFF.
File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
Patch Set #54, Line 33: gpio_get(DGPU_PRESENT)
I haven't heard of any policy against wanting to do things properly :) […]
Of course. No idea what I thought could possibly be an issue (their copyright couldn't prevent our use)
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