Zoey Wu has uploaded this change for review.

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Change DDR4 Interleave to Non-Interleave

Signed-off-by: zoey wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: I2e84927b7296c565e6be25b09c5f64a338af51d0
---
A src/mainboard/google/brya/variants/moli/Makefile.inc
A src/mainboard/google/brya/variants/moli/memory.c
2 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/62469/1

diff --git a/src/mainboard/google/brya/variants/moli/Makefile.inc b/src/mainboard/google/brya/variants/moli/Makefile.inc
new file mode 100644
index 0000000..f5c5897
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moli/Makefile.inc
@@ -0,0 +1,7 @@
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/moli/memory.c b/src/mainboard/google/brya/variants/moli/memory.c
new file mode 100644
index 0000000..20ec20b
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moli/memory.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr4_mem_config = {
+	
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+
+};

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