Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu.
Hello Yidi Lin,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/84932?usp=email
to review the following change.
Change subject: Rauru: Configure TPM ......................................................................
Rauru: Configure TPM
1. Add TPM support 2. Configure I2C speed to I2C_SPEED_FAST_PLUS 3. Pass GPIO_GSC_AP_INT_ODL to the payload 4. Configure IRQ type to IRQ_TYPE_LEVEL_LOW for now
Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Signed-off-by: Yidi Lin yidilin@chromium.org --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/bootblock.c M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h 4 files changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84932/1
diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index 011beed..fc1e839 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -10,7 +10,6 @@ config VBOOT select VBOOT_VBNV_FLASH select EC_GOOGLE_CHROMEEC_SWITCHES - select VBOOT_MOCK_SECDATA
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -24,6 +23,9 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI + select I2C_TPM if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT + select TPM_GOOGLE_TI50 if VBOOT
config MAINBOARD_DIR string @@ -41,4 +43,13 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x1 + +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + endif diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c index bbebf52..234c89b 100644 --- a/src/mainboard/google/rauru/bootblock.c +++ b/src/mainboard/google/rauru/bootblock.c @@ -2,6 +2,8 @@
#include <bootblock_common.h> #include <gpio.h> +#include <soc/gpio.h> +#include <soc/i2c.h> #include <soc/pcie.h> #include <soc/spi.h>
@@ -17,8 +19,10 @@ if (CONFIG(PCI)) mtk_pcie_pre_init();
+ mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST_PLUS); mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_snfc_init(); usb3_hub_reset(); setup_chromeos_gpios(); + gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_LEVEL_LOW); } diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index a24995f..de36114 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -1,13 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <boot/coreboot_tables.h> +#include <drivers/tpm/cr50.h> #include <gpio.h> +#include <console/console.h>
#include "gpio.h"
void setup_chromeos_gpios(void) { gpio_input(GPIO_EC_AP_INT_ODL); + gpio_input(GPIO_GSC_AP_INT_ODL); gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0); gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0); gpio_output(GPIO_BEEP_ON_OD, 0); @@ -24,6 +27,12 @@ { GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable" }, { GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt" }, { GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable" }, + { GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt" }, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } + +int cr50_plat_irq_status(void) +{ + return gpio_eint_poll(GPIO_GSC_AP_INT_ODL); +} diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index b8c9a82..d97b38d 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -7,6 +7,7 @@
#define GPIO_BEEP_ON_OD GPIO(PERIPHERAL_EN1) #define GPIO_EN_SPKR GPIO(PERIPHERAL_EN0) +#define GPIO_GSC_AP_INT_ODL GPIO(EINT18) #define GPIO_EC_AP_INT_ODL GPIO(EINT19) #define GPIO_XHCI_INIT_DONE GPIO(EINT28) #define GPIO_AP_EC_WARM_RST_REQ GPIO(EINT29)