Ronak Kanabar has uploaded this change for review.
soc/intel/tigerlake: Correct order of "RUN_FSP_GOP" check
coreboot was programming DDI_BUF_CTL in case GOP/VBIOS is
not executed. When RUN_FSP_GOP config is selected, GOP will
be executed and we don't need to program DDI_BUF_CTL.
Hence moving the check before DDI_BUF_CTL programming
In case display is not connected, it may cause hang since GOP
is also programming DDI_BUF_CTL before coreboot graphics_init
call.
BUG=None
BRANCH=None
TEST=checked jslrvp and tglrvp compilation and boot.
Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
---
M src/soc/intel/tigerlake/graphics.c
1 file changed, 12 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/39313/1
diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c
index c215384..86e9fca 100644
--- a/src/soc/intel/tigerlake/graphics.c
+++ b/src/soc/intel/tigerlake/graphics.c
@@ -45,6 +45,18 @@
return;
/*
+ * GFX PEIM module inside FSP binary is taking care of graphics
+ * initialization based on RUN_FSP_GOP Kconfig
+ * option and input VBT file. Hence no need to load/execute legacy VGA
+ * OpROM in order to initialize GFX.
+ *
+ * In case of non-FSP solution, SoC need to select VGA_ROM_RUN
+ * Kconfig to perform GFX initialization through VGA OpRom.
+ */
+ if (CONFIG(RUN_FSP_GOP))
+ return;
+
+ /*
* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
* This will allow the kernel to use 4-lane eDP links properly
* if the VBIOS or GOP driver do not execute.
@@ -56,18 +68,6 @@
graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
}
- /*
- * GFX PEIM module inside FSP binary is taking care of graphics
- * initialization based on RUN_FSP_GOP Kconfig
- * option and input VBT file. Hence no need to load/execute legacy VGA
- * OpROM in order to initialize GFX.
- *
- * In case of non-FSP solution, SoC need to select VGA_ROM_RUN
- * Kconfig to perform GFX initialization through VGA OpRom.
- */
- if (CONFIG(RUN_FSP_GOP))
- return;
-
/* IGD needs to Bus Master */
uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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