[coreboot-gerrit] [L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email )

Change subject: soc/intel/xeon_sp: Redesign resource allocation
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Patch Set 4:

(1 comment)

File src/soc/intel/xeon_sp/chip_common.c:

https://review.coreboot.org/c/coreboot/+/78327/comment/e261a5d1_bf3b8a6c :
PS4, Line 112: 	.scan_bus = non_iio_pci_domain_scan_bus,
> For non_iiostack_pci_domain_ops, maybe we could have similar renaming as well?

Don't these integrated devices implement the upper layers of PCI (i.e. show as a
PCI device to software)? Then it would be quite irritating to call them non-PCI.
How about `integrated_iio_stack_...`?