Attention is currently required from: Bora Guvendik, Felix Singer, Karthik Ramasubramanian, Shelley Chen.
1 comment:
File src/mainboard/google/brox/variants/baseboard/brox/gpio.c:
Patch Set #3, Line 188: PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG),
Ashish, are you saying that if we config GPP_D0 with PAD_CFG_APIC_LOCK it would prevent the IRQ 44 c […]
Yes, BUT the PAD_CFG_GPI_INT and PAD_CFG_APIC_LOCK macros are 2 different purposes with different flag settings. This one PAD_CFG_GPI_INT doesn't have an IOAPIC flag. Whereas this one PAD_CFG_APIC_LOCK does. Due to that IOAPIC flag namely PAD_CFG0_ROUTE_IOAPIC, the pin polarity will be set, which is not required for intpin GPP_D0 in this case. See gpio.c/gpio_defs.h for more details.
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