Attention is currently required from: Patrick Rudolph.

Tim Wawrzynczak has uploaded this change for review.

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soc/intel/alderlake: Switch to runtime generation of Intel Power Engine

The pep.asl file is being obsoleted by runtime generation, therefore
switch alderlake boards to this method.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/acpi/southbridge.asl
M src/soc/intel/alderlake/pmc.c
3 files changed, 6 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/56006/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 3c49748..089daf9 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -50,6 +50,8 @@
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
+ select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
+ select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl
index 59bcf74..8300c23 100644
--- a/src/soc/intel/alderlake/acpi/southbridge.asl
+++ b/src/soc/intel/alderlake/acpi/southbridge.asl
@@ -38,8 +38,5 @@
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>

-/* Intel Power Engine Plug-in */
-#include <soc/intel/common/block/acpi/acpi/pep.asl>
-
/* GbE 0:1f.6 */
#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c
index dd88b1d..df75396 100644
--- a/src/soc/intel/alderlake/pmc.c
+++ b/src/soc/intel/alderlake/pmc.c
@@ -11,6 +11,7 @@
#include <device/mmio.h>
#include <device/device.h>
#include <drivers/intel/pmc_mux/chip.h>
+#include <intelblocks/acpi.h>
#include <intelblocks/pmc.h>
#include <intelblocks/pmc_ipc.h>
#include <intelblocks/pmclib.h>
@@ -122,6 +123,9 @@
acpigen_pop_len(); /* PMC Device */
acpigen_pop_len(); /* Scope */

+ /* Add Intel Power Engine device */
+ generate_acpi_power_engine(dev);
+
printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name,
dev_path(dev));
}

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834
Gerrit-Change-Number: 56006
Gerrit-PatchSet: 1
Gerrit-Owner: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Attention: Patrick Rudolph <siro@das-labor.org>
Gerrit-MessageType: newchange