Kane Chen (kane.chen@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15951
-gerrit
commit 94039e1d9b776a3e77c4ed8fb0a84835621a82a8 Author: Kane Chen kane.chen@intel.com Date: Thu Jul 28 19:41:15 2016 +0800
google/reef: Add pull up 20K for LPC SERIRQ
per hw team's check and info from EDS, this pin need to be pu 20K. Otherwise SoC may not notice interrupt request from EC over LPC because SERIRQ line is floating.
BUG=chrome-os-partner:55586 BRANCH=none TEST=boot ok and Quanta factory help to verify the keyboard issue is gone
Signed-off-by: Kane Chen kane.chen@intel.com Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a --- src/mainboard/google/reef/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 88f5cdc..1e88215 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -77,7 +77,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */
/* LPC */ - PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), /* LPC_AD0 */