[coreboot-gerrit] Change in coreboot[master]: amd/agesa/family14, 15 & 16: Remove unnecessary whitespace

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23481

Change subject: amd/agesa/family14,15 & 16: Remove unnecessary whitespace
......................................................................

amd/agesa/family14,15 & 16: Remove unnecessary whitespace

Change-Id: I9495b47a85a6fb9d8d06d9a82c0444b794ec4933
Signed-off-by: Elyes HAOUAS 
---
M src/cpu/amd/agesa/family14/model_14_init.c
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/cpu/amd/agesa/family16kb/model_16_init.c
3 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/23481/1

diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index a03516d..2f7abd8 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -42,7 +42,7 @@
 #endif
    printk(BIOS_DEBUG, "Model 14 Init.\n");

-	disable_cache ();
+	disable_cache();
    /*
     * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
     * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14.
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index e0bff4f..5f2c603 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -46,7 +46,7 @@
    //x86_enable_cache();
    //amd_setup_mtrrs();
    //x86_mtrr_check();
-	disable_cache ();
+	disable_cache();
    /* Enable access to AMD RdDram and WrDram extension bits */
    msr = rdmsr(SYSCFG_MSR);
    msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index d49216a..aa56881 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -44,7 +44,7 @@
    //x86_enable_cache();
    //amd_setup_mtrrs();
    //x86_mtrr_check();
-	disable_cache ();
+	disable_cache();
    /* Enable access to AMD RdDram and WrDram extension bits */
    msr = rdmsr(SYSCFG_MSR);
    msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;