Nico Huber would like Patrick Rudolph and Lance Zhao to review this change.
soc/intel: Replace UART_BASE() and friends with a Kconfig
Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident
on APL at least. It is used outside of soc/intel/ scope, e.g. to con-
figure SeaBIOS.
As we only ever configure a single UART for the coreboot console, we
don't need different addresses for each possible UART. Which saves
us a lot of code.
Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309
Signed-off-by: Nico Huber <nico.h@gmx.de>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/include/soc/iomap.h
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/include/soc/iomap.h
M src/soc/intel/common/acpi/acpi_debug.asl
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/include/soc/iomap.h
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/include/soc/iomap.h
10 files changed, 25 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/33098/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 217d1ea..1f819ea 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -361,6 +361,11 @@
int
default 100
+config CONSOLE_UART_BASE_ADDRESS
+ hex
+ default 0xddffc000
+ depends on INTEL_LPSS_UART_FOR_CONSOLE
+
config APL_SKIP_SET_POWER_LIMITS
bool
default n
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 8e2986d..4b82365 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -58,12 +58,4 @@
#define EARLY_I2C_BASE_ADDRESS 0xfe020000
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
-#define UART_BASE_SIZE 0x1000
-
-#define UART_BASE_0_ADDRESS 0xddffc000
-/* UART BARs are 4KB in size */
-#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \
- UART_BASE_SIZE * (x)))
-#define UART_BASE(x) UART_BASE_0_ADDR(x)
-
#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index e524275..76906b2 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -223,6 +223,11 @@
default 4 if SOC_INTEL_CANNONLAKE_PCH_H
default 6
+config CONSOLE_UART_BASE_ADDRESS
+ hex
+ default 0xfe032000
+ depends on INTEL_LPSS_UART_FOR_CONSOLE
+
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index 100bd11..1ebaf3f 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -29,14 +29,6 @@
#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
-#define UART_BASE_SIZE 0x1000
-
-#define UART_BASE_0_ADDRESS 0xfe032000
-/* Both UART BAR 0 and 1 are 4KB in size */
-#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \
- UART_BASE_SIZE * (x)))
-#define UART_BASE(x) UART_BASE_0_ADDR(x)
-
#define EARLY_I2C_BASE_ADDRESS 0xfe040000
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl
index 6c52bbf..0c0be15 100644
--- a/src/soc/intel/common/acpi/acpi_debug.asl
+++ b/src/soc/intel/common/acpi/acpi_debug.asl
@@ -59,7 +59,7 @@
#if CONFIG(DRIVERS_UART_8250MEM_32)
OperationRegion (UBAR, SystemMemory,
- UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE), 24)
+ CONFIG_CONSOLE_UART_BASE_ADDRESS, 24)
Field (UBAR, AnyAcc, NoLock, Preserve)
{
TDR, 8, /* Transmit Data Register BAR + 0x000 */
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 84ba1ee..9d820ff 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -47,7 +47,7 @@
uintptr_t uart_platform_base(int idx)
{
if (idx == CONFIG_UART_FOR_CONSOLE)
- return UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
+ return CONFIG_CONSOLE_UART_BASE_ADDRESS;
return 0;
}
#endif
@@ -137,8 +137,7 @@
void uart_bootblock_init(void)
{
/* Program UART BAR0, command, reset and clock register */
- uart_common_init(uart_get_device(),
- UART_BASE(CONFIG_UART_FOR_CONSOLE));
+ uart_common_init(uart_get_device(), CONFIG_CONSOLE_UART_BASE_ADDRESS);
/* Configure the 2 pads per UART. */
uart_configure_gpio_pads();
@@ -155,8 +154,8 @@
uart_is_debug_controller(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
/* Need to set the base and size for the resource allocator. */
- res->base = UART_BASE(CONFIG_UART_FOR_CONSOLE);
- res->size = UART_BASE_SIZE;
+ res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
+ res->size = 0x1000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
}
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index a4b46ba..052e37d 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -138,6 +138,11 @@
int
default 3
+config CONSOLE_UART_BASE_ADDRESS
+ hex
+ default 0xfe032000
+ depends on INTEL_LPSS_UART_FOR_CONSOLE
+
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h
index 7c42b57..218b8bf 100644
--- a/src/soc/intel/icelake/include/soc/iomap.h
+++ b/src/soc/intel/icelake/include/soc/iomap.h
@@ -28,14 +28,6 @@
#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
-#define UART_BASE_SIZE 0x1000
-
-#define UART_BASE_0_ADDRESS 0xfe032000
-/* Both UART BAR 0 and 1 are 4KB in size */
-#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \
- UART_BASE_SIZE * (x)))
-#define UART_BASE(x) UART_BASE_0_ADDR(x)
-
#define EARLY_I2C_BASE_ADDRESS 0xfe040000
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index fcfe2b6..626b5f8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -289,6 +289,11 @@
int
default 100
+config CONSOLE_UART_BASE_ADDRESS
+ hex
+ default 0xfe030000
+ depends on INTEL_LPSS_UART_FOR_CONSOLE
+
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index 628a272..c73d766 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -25,13 +25,6 @@
#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
#define PCH_PRESERVED_BASE_SIZE 0x02000000
-#define UART_BASE_SIZE 0x1000
-#define UART_BASE_0_ADDRESS 0xfe030000
-/* Both UART BAR 0 and 1 are 4KB in size */
-#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \
- UART_BASE_SIZE * (x)))
-#define UART_BASE(x) UART_BASE_0_ADDR(x)
-
#define EARLY_I2C_BASE_ADDRESS 0xfe040000
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
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