Patch Set #1, Line 51:
resource->flags |= IORESOURCE_IO;
In order for the hot-plugging of devices and busses to work, we need to reserve MMIO and IO space fo […]
I understand the requirements in order to set up a pci topology. However, my question was bout the assumptions that are being made about the OS or program running after coreboot. This patch is assuming a static allocation is sufficient when it's definitely not going to be correct 100% of the time.
Patch Set #1, Line 73:
haven't looked very closely at the code, but what does happen if there are devices already connected […]
That's assuming thunderbolt links are already provisioned and pcie tunneling is happening. Otherwise one couldn't see the devices on the other side of the link.
Patch Set #1, Line 80:
slot = alloc_dev(dev->link_list, &slot_path);
IIRC the 256MiB was what the vendor firmware does; not sure if this is mandated by the TB spec. 256MiB prefetchable MMIO space sounds reasonable to me; 256MiB non-prefetchable MMIO sounds rather big to me though (and the non-prefetchable can't be mapped above 4G)
What are you basing your assumptions on? Video cards and small BARs on a nic?
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