Attention is currently required from: Raul Rangel, Nico Huber, Michał Żygowski, Subrata Banik, Reka Norman, Michał Kopeć, Angel Pons, Arthur Heymans, Felix Held.
Subrata Banik uploaded patch set #23 to the change originally created by Arthur Heymans.
cpu/x86/cache: CLFLUSH programs to memory before running
When cbmem is initialized in romstage and postcar placed in the stage
cache + cbmem where it is run, the assumption is made that these are
all in UC memory such that calling INVD in postcar is OK.
For performance reasons (e.g. postcar decompression) it is desirable
to cache cbmem and the stage cache during romstage.
Another reason is that AGESA sets up MTRR during romstage to cache all
dram, which is currently worked around by using additional MTRR's to
make that UC.
TESTED on asus/p5ql-em, up/squared on both regular and S3 resume
bootpath. Sometimes there are minimal performance improvements
when cbmem is cached (few ms).
Signed-off-by: Arthur Heymans <firstname.lastname@example.org>
6 files changed, 117 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37196/23
To view, visit change 37196. To unsubscribe, or for help writing mail filters, visit settings.