Elyes Haouas has uploaded this change for review.
cbmem_top: Change the return value to uintptr_t
Get rid of a lot of casts.
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
---
M src/drivers/amd/agesa/mtrr_fixme.c
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp2_0/hob_verify.c
M src/include/cbmem.h
M src/lib/imd_cbmem.c
M src/northbridge/intel/gm45/memmap.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/haswell/memmap.c
M src/northbridge/intel/i440bx/memmap.c
M src/northbridge/intel/i945/memmap.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/memmap.c
M src/northbridge/intel/pineview/memmap.c
M src/northbridge/intel/sandybridge/memmap.c
M src/northbridge/intel/x4x/memmap.c
M src/northbridge/intel/x4x/northbridge.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/glinda/root_complex.c
M src/soc/amd/mendocino/root_complex.c
M src/soc/amd/morgana/root_complex.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/stoneyridge/memmap.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/baytrail/memmap.c
M src/soc/intel/broadwell/memmap.c
M src/soc/intel/common/block/systemagent/memmap.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/uncore.c
34 files changed, 53 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/69163/1
diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c
index 3aef898..bc72458 100644
--- a/src/drivers/amd/agesa/mtrr_fixme.c
+++ b/src/drivers/amd/agesa/mtrr_fixme.c
@@ -45,7 +45,7 @@
* writeback possible.
*/
- uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ uintptr_t top_of_ram = cbmem_top();
top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB);
set_range_uc(top_of_ram - 4 * MiB, 4 * MiB);
@@ -79,7 +79,7 @@
* speed make them WB after CAR teardown.
*/
if (s3resume) {
- uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ uintptr_t top_of_ram = cbmem_top();
top_of_ram = ALIGN_DOWN(top_of_ram, 4 * MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 4 * MiB, 4 * MiB,
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index fc05b91..e9bfafa 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -17,7 +17,7 @@
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations. */
- top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK);
}
diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c
index ec526e8..c0ee2b8 100644
--- a/src/drivers/intel/fsp2_0/hob_verify.c
+++ b/src/drivers/intel/fsp2_0/hob_verify.c
@@ -43,7 +43,7 @@
die("Space between FSP reserved region and BIOS TOLUM!\n");
}
- if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) {
+ if (range_entry_end(&tolum) != cbmem_top()) {
printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n",
range_entry_end(&tolum), cbmem_top());
die("Space between cbmem_top and BIOS TOLUM!\n");
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 911291a..6e8f33a 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -57,7 +57,7 @@
/* The assumption is made that the result of cbmem_top_romstage fits in the size
of uintptr_t in the ramstage. */
extern uintptr_t _cbmem_top_ptr;
-void *cbmem_top(void);
+uintptr_t cbmem_top(void);
/* With CONFIG_RAMSTAGE_CBMEM_TOP_ARG set, the result of cbmem_top is passed via
* calling arguments to the next stage and saved in the global _cbmem_top_ptr
* global variable. Only a romstage callback needs to be implemented by the
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index 91c8621..9c01f12 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -15,17 +15,17 @@
static struct imd imd;
-void *cbmem_top(void)
+uintptr_t cbmem_top(void)
{
if (ENV_CREATES_CBMEM) {
static uintptr_t top;
if (top)
- return (void *)top;
+ return top;
top = cbmem_top_chipset();
- return (void *)top;
+ return top;
}
if (ENV_POSTCAR || ENV_RAMSTAGE)
- return (void *)_cbmem_top_ptr;
+ return _cbmem_top_ptr;
dead_code();
}
@@ -55,7 +55,7 @@
/* The test is only effective on X86 and when address hits UC memory. */
if (ENV_X86)
- quick_ram_check_or_die((uintptr_t)cbmem_top() - sizeof(u32));
+ quick_ram_check_or_die(cbmem_top() - sizeof(u32));
}
void cbmem_initialize_empty_id_size(u32 id, u64 size)
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 2ba7c80..74bda32 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -123,7 +123,7 @@
/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
* RAM to cover both cbmem as the TSEG region.
*/
- top_of_ram = (uintptr_t)cbmem_top();
+ top_of_ram = cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index df5526c..cf289b9 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -93,7 +93,7 @@
/* cbmem_top can be shifted downwards due to alignment.
Mark the region between cbmem_top and tomk as unusable */
- delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10);
+ delta_cbmem = tomk - (cbmem_top() >> 10);
tomk -= delta_cbmem;
uma_sizek += delta_cbmem;
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 6b75caa..c786dc9 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -75,6 +75,6 @@
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
- top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB);
+ top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
}
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 5cee1b4..fb79868 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -56,7 +56,7 @@
uintptr_t top_of_ram;
/* Cache CBMEM region as WB. */
- top_of_ram = (uintptr_t)cbmem_top();
+ top_of_ram = cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 96dee76..af23c5f 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -87,7 +87,7 @@
/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
* RAM to cover both cbmem as the TSEG region.
*/
- top_of_ram = (uintptr_t)cbmem_top();
+ top_of_ram = cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 3c5603c..41accab 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -62,7 +62,7 @@
/* cbmem_top can be shifted downwards due to alignment.
Mark the region between cbmem_top and tomk as unusable */
- cbmem_topk = ((uintptr_t)cbmem_top() / KiB);
+ cbmem_topk = (cbmem_top() / KiB);
delta_cbmem = tomk_stolen - cbmem_topk;
tomk_stolen -= delta_cbmem;
diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c
index bdb76c1..e089144 100644
--- a/src/northbridge/intel/ironlake/memmap.c
+++ b/src/northbridge/intel/ironlake/memmap.c
@@ -41,7 +41,7 @@
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
- top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
}
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 55d7046..f43120c 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -93,7 +93,7 @@
* Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both
* CBMEM and the TSEG region.
*/
- top_of_ram = (uintptr_t)cbmem_top();
+ top_of_ram = cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(),
MTRR_TYPE_WRBACK);
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index ac95ab5..e99f2ee 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -67,7 +67,7 @@
void fill_postcar_frame(struct postcar_frame *pcf)
{
- uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ uintptr_t top_of_ram = cbmem_top();
/*
* Cache 8MiB below the top of ram. On sandybridge systems the top of
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 0b085cf..4aa2a33 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -89,7 +89,7 @@
/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
* RAM to cover both cbmem as the TSEG region.
*/
- top_of_ram = (uintptr_t)cbmem_top();
+ top_of_ram = cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index ac276b6..74226bc 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -70,7 +70,7 @@
/* cbmem_top can be shifted downwards due to alignment.
Mark the region between cbmem_top and tomk as unusable */
- delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10);
+ delta_cbmem = tomk - (cbmem_top() >> 10);
tomk -= delta_cbmem;
uma_sizek += delta_cbmem;
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index ed919b1..cec0626 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -101,7 +101,7 @@
*/
static void read_resources(struct device *dev)
{
- uint32_t mem_usable = (uintptr_t)cbmem_top();
+ uintptr_t mem_usable = cbmem_top();
unsigned int idx = 0;
const struct hob_header *hob = fsp_get_hob_list();
const struct hob_resource *res;
diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c
index ef6c630..d088022 100644
--- a/src/soc/amd/glinda/root_complex.c
+++ b/src/soc/amd/glinda/root_complex.c
@@ -116,7 +116,7 @@
*/
static void read_resources(struct device *dev)
{
- uint32_t mem_usable = (uintptr_t)cbmem_top();
+ uintptr_t mem_usable = cbmem_top();
unsigned int idx = 0;
const struct hob_header *hob = fsp_get_hob_list();
const struct hob_resource *res;
diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c
index 6768613..24edd0f7 100644
--- a/src/soc/amd/mendocino/root_complex.c
+++ b/src/soc/amd/mendocino/root_complex.c
@@ -116,7 +116,7 @@
*/
static void read_resources(struct device *dev)
{
- uint32_t mem_usable = (uintptr_t)cbmem_top();
+ uintptr_t mem_usable = cbmem_top();
unsigned int idx = 0;
const struct hob_header *hob = fsp_get_hob_list();
const struct hob_resource *res;
diff --git a/src/soc/amd/morgana/root_complex.c b/src/soc/amd/morgana/root_complex.c
index 88bcca7..b0fdced 100644
--- a/src/soc/amd/morgana/root_complex.c
+++ b/src/soc/amd/morgana/root_complex.c
@@ -116,7 +116,7 @@
*/
static void read_resources(struct device *dev)
{
- uint32_t mem_usable = (uintptr_t)cbmem_top();
+ uintptr_t mem_usable = cbmem_top();
unsigned int idx = 0;
const struct hob_header *hob = fsp_get_hob_list();
const struct hob_resource *res;
diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c
index d53643e..247ca1f 100644
--- a/src/soc/amd/picasso/root_complex.c
+++ b/src/soc/amd/picasso/root_complex.c
@@ -101,7 +101,7 @@
*/
static void read_resources(struct device *dev)
{
- uint32_t mem_usable = (uintptr_t)cbmem_top();
+ uintptr_t mem_usable = cbmem_top();
unsigned int idx = 0;
const struct hob_header *hob = fsp_get_hob_list();
const struct hob_resource *res;
diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c
index 8de3515..176b7e9 100644
--- a/src/soc/amd/stoneyridge/memmap.c
+++ b/src/soc/amd/stoneyridge/memmap.c
@@ -26,7 +26,7 @@
static uintptr_t smm_region_start(void)
{
- return (uintptr_t)cbmem_top();
+ return cbmem_top();
}
static size_t smm_region_size(void)
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 7e93896..c1adf33 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -376,7 +376,7 @@
{
uint64_t uma_base = get_uma_base();
uint32_t uma_size = get_uma_size();
- uint32_t mem_useable = (uintptr_t)cbmem_top();
+ uintptr_t mem_useable = cbmem_top();
msr_t tom = rdmsr(TOP_MEM);
msr_t high_tom = rdmsr(TOP_MEM2);
uint64_t high_mem_useable;
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 7d1124a..ceeaeb6 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -123,7 +123,7 @@
void fill_postcar_frame(struct postcar_frame *pcf)
{
- uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ uintptr_t top_of_ram = cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index 43b96c1..8e3b767 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -35,7 +35,7 @@
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
- top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
}
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 98c8016..f94c54b 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -53,7 +53,7 @@
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
- top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
}
diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c
index 97344cd..ee3b51a 100644
--- a/src/soc/intel/common/block/systemagent/memmap.c
+++ b/src/soc/intel/common/block/systemagent/memmap.c
@@ -59,7 +59,7 @@
void fill_postcar_frame(struct postcar_frame *pcf)
{
/* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */
- uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB);
+ uintptr_t top_of_ram = ALIGN_UP(cbmem_top(), 8 * MiB);
/*
* We need to make sure ramstage will be run cached. At this
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index e74c118..d5465c8 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -191,7 +191,7 @@
uintptr_t top_of_ram;
int index = *resource_count;
- top_of_ram = (uintptr_t)cbmem_top();
+ top_of_ram = cbmem_top();
/* 0 - > 0xa0000 */
ram_from_to(dev, index++, 0, 0xa0000);
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index 399bb64..d37834c 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -55,7 +55,7 @@
void soc_fill_gnvs(struct global_nvs *gnvs)
{
/* Top of Low Memory (start of resource allocation) */
- gnvs->tolm = (uintptr_t)cbmem_top();
+ gnvs->tolm = cbmem_top();
/* MMIO Low/High & TSEG base and length */
gnvs->mmiob = (u32)get_top_of_low_memory();
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index f607d0f..0ad4c5b 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -48,7 +48,7 @@
* location of ramstage in cbmem is not known. Instruct postcar to cache
* 16 megs under cbmem top which is a safe bet to cover ramstage.
*/
- top_of_ram = (uintptr_t)cbmem_top();
+ top_of_ram = cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
MTRR_TYPE_WRBACK);
diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c
index 29953a6..a28343f 100644
--- a/src/soc/intel/denverton_ns/systemagent.c
+++ b/src/soc/intel/denverton_ns/systemagent.c
@@ -232,7 +232,7 @@
* PCI_BASE_ADDRESS_0.
*/
index = 0;
- top_of_ram = (uintptr_t)cbmem_top();
+ top_of_ram = cbmem_top();
/* 0 - > 0xa0000 */
base_k = 0;
diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c
index f1e5c63..7c83771 100644
--- a/src/soc/intel/quark/northcluster.c
+++ b/src/soc/intel/quark/northcluster.c
@@ -28,10 +28,10 @@
reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
/* 0x100000 -> cbmem_top - cacheable and usable */
- ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top());
+ ram_from_to(dev, index++, 1 * MiB, cbmem_top());
/* cbmem_top -> 0xc0000000 - reserved */
- reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), 0xc0000000);
+ reserved_ram_from_to(dev, index++, cbmem_top(), 0xc0000000);
/* 0xc0000000 -> 4GiB is mmio. */
mmio_from_to(dev, index++, 0xc0000000, 4ull * GiB);
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
index c256484..54e8c10 100644
--- a/src/soc/intel/xeon_sp/memmap.c
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -29,7 +29,7 @@
void fill_postcar_frame(struct postcar_frame *pcf)
{
- const uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ const uintptr_t top_of_ram = cbmem_top();
uintptr_t cbmem_base;
size_t cbmem_size;
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 1a60b60..62e7ae2 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -93,7 +93,7 @@
static void configure_dpr(struct device *dev)
{
- const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB;
+ const uintptr_t cbmem_top_mb = ALIGN_UP(cbmem_top(), MiB) / MiB;
union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
/* The DPR lock bit has to be set sufficiently early. It looks like
@@ -183,7 +183,7 @@
LOG_RESOURCE("legacy_ram", dev, res);
/* 1MB -> top_of_ram i.e., cbmem_top */
- res = ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top());
+ res = ram_from_to(dev, index++, 1 * MiB, cbmem_top());
LOG_RESOURCE("low_ram", dev, res);
/* Mark TSEG/SMM region as reserved */
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