Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30272
to look at the new patch set (#7).
Change subject: nb/intel/haswell: Add support for PCIe graphics ......................................................................
nb/intel/haswell: Add support for PCIe graphics
PEG link training is started in early romstage, before the MRC runs. The MRC will then set (and lock) GGC, and, if there is a device of VGA class present in a PEG slot, disable the IGD:
Before the MRC: GGC = 0x0208, DEVEN = 0x00000039. After the MRC: GGC = 0x0003, DEVEN = 0x00000029.
If the IGD needs to be kept enabled, the PEG device is hidden while the MRC runs. The link training is able to continue even while the PEG device is hidden.
Only PEG2 is supported. An extra (unknown) training sequence is said to be needed for PEG3.
The ACPI _PRT method is not yet generated, so legacy interrupt routing doesn't work for devices with multiple functions.
Tested on an ASRock H81M-HDS. Using an x1 PCIe card in the PEG slot works fine. Using a Radeon HD 6450 graphics card also works under GNU/Linux, both using the display from the Radeon HD 6450, and when the IGD is used for display output and `DRI_PRIME=1` is set.
Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e Signed-off-by: Tristan Corrick tristan@corrick.kiwi --- M src/cpu/intel/haswell/romstage.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/haswell.h 3 files changed, 83 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30272/7