Subrata Banik has uploaded this change for review.
soc/intel/cannonlake: Speed up postcar loading using intermediate caching
This patch ensures intermediate caching is enabled to speed up
loading and decompression of next stage as we are still in romstage
and car tear down will be handled by next stage at its entry.
TEST=cbmem -t shows ~2-4ms time savings in warm reboot case with this
CL.
Change-Id: I3ba63887acb5c4bdeaf3e21c24fb0e631362962c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/cannonlake/romstage/romstage.c
1 file changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/34791/1
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 94b9899..04a9d53 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -127,6 +127,21 @@
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
+/*
+ * Make sure we are enabling intermediate caching to speed up next stage
+ * (postcar/romstage) loading and decompression as we are still in romstage
+ * and car tear down will be handled by next stage at its entry.
+ */
+static void enable_ramstage_caching(uintptr_t base, size_t size)
+{
+ int mtrr = get_free_var_mtrr();
+
+ if (mtrr == -1)
+ return;
+
+ set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
+}
+
asmlinkage void car_stage_entry(void)
{
bool s3wake;
@@ -160,6 +175,8 @@
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+ /* enabling intermediate caching */
+ enable_ramstage_caching(top_of_ram, 16*MiB);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
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