Patrick Georgi submitted this change.
sb/intel/bd82x6x: Do cosmetic fixes
Make the code follow the coding style, and reflow things that fit in 96
characters.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: I6e0acdc9c21d4b416597dc776bd9abab12bff4a0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
M src/southbridge/intel/bd82x6x/early_pch.c
M src/southbridge/intel/bd82x6x/early_rcba.c
M src/southbridge/intel/bd82x6x/early_thermal.c
3 files changed, 22 insertions(+), 33 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 530f11a..bd507c4 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -19,15 +19,13 @@
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
-static void
-wait_iobp(void)
+static void wait_iobp(void)
{
while (RCBA8(IOBPS) & 1)
; // implement timeout?
}
-static u32
-read_iobp(u32 address)
+static u32 read_iobp(u32 address)
{
u32 ret;
@@ -40,8 +38,7 @@
return ret;
}
-static void
-write_iobp(u32 address, u32 val)
+static void write_iobp(u32 address, u32 val)
{
/* this function was probably pch_iobp_update with the andvalue
* being 0. So either the IOBP read can be removed or this function
@@ -137,11 +134,9 @@
;
}
-void
-early_pch_init_native (void)
+void early_pch_init_native(void)
{
- pci_write_config8 (SOUTHBRIDGE, 0xa6,
- pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
+ pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2);
RCBA32(CIR1) = 0x00109000;
RCBA32(REC); // !!! = 0x00000000
@@ -278,9 +273,8 @@
* - 0x3f8-0x3ff COMA
*/
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
- | MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
- | COMB_LPC_EN | COMA_LPC_EN);
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
const struct device *dev = pcidev_on_root(0x1f, 0);
const struct southbridge_intel_bd82x6x_config *config = NULL;
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
index 915a935..61877bb 100644
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -5,8 +5,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include "pch.h"
-void
-southbridge_configure_default_intmap(void)
+void southbridge_configure_default_intmap(void)
{
/*
* For the PCH internal PCI functions, provide a reasonable
@@ -83,8 +82,7 @@
(void) RCBA16(OIC);
}
-void
-southbridge_rcba_config(void)
+void southbridge_rcba_config(void)
{
RCBA32(FD) = PCH_DISABLE_ALWAYS;
}
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c
index ac7a3a4..e73f3a5 100644
--- a/src/southbridge/intel/bd82x6x/early_thermal.c
+++ b/src/southbridge/intel/bd82x6x/early_thermal.c
@@ -36,34 +36,31 @@
pci_write_config32(dev, 0x44, 0x0);
/* Activate temporary BAR. */
- pci_write_config32(dev, 0x40,
- pci_read_config32(dev, 0x40) | 5);
+ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5);
- write16p (0x40000004, 0x3a2b);
- write8p (0x4000000c, 0xff);
- write8p (0x4000000d, 0x00);
- write8p (0x4000000e, 0x40);
- write8p (0x40000082, 0x00);
- write8p (0x40000001, 0xba);
+ write16p(0x40000004, 0x3a2b);
+ write8p(0x4000000c, 0xff);
+ write8p(0x4000000d, 0x00);
+ write8p(0x4000000e, 0x40);
+ write8p(0x40000082, 0x00);
+ write8p(0x40000001, 0xba);
/* Perform init. */
/* Configure TJmax. */
msr = rdmsr(MSR_TEMPERATURE_TARGET);
write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
- /* Northbridge temperature slope and offset. */
+ /* Northbridge temperature slope and offset */
write16p(0x40000016, 0x808c);
- write16p (0x40000014, 0xde87);
+ write16p(0x40000014, 0xde87);
- /* Enable thermal data reporting, processor, PCH and northbridge. */
+ /* Enable thermal data reporting, processor, PCH and northbridge */
write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0);
- /* Disable temporary BAR. */
- pci_write_config32(dev, 0x40,
- pci_read_config32(dev, 0x40) & ~1);
+ /* Disable temporary BAR */
+ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1);
pci_write_config32(dev, 0x40, 0);
- write32 (DEFAULT_RCBA + 0x38b0,
- (read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c);
+ write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c);
}
To view, visit change 41110. To unsubscribe, or for help writing mail filters, visit settings.