Angel Pons has uploaded this change for review.
[WIP, HACK] broadwell: make uart support build again
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@ @
@ DO NOT MERGE AS-IS! @
@ @
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
I am fully aware this is an atrociously hideous kludge. Moreover, this
change won't be properly build-tested by Mr. Jenkins, and it has not
been tested on real hardware either. It only exists for backup purposes.
Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/soc/intel/broadwell/Makefile.inc
M src/soc/intel/broadwell/romstage/uart.c
M src/soc/intel/broadwell/serialio.c
3 files changed, 17 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37553/1
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 03aa3fb..61b62c8 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -9,6 +9,7 @@
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/intel/common
+bootblock-y += romstage/uart.c
bootblock-y += bootblock/cpu.c
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/systemagent.c
@@ -16,6 +17,9 @@
bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S
bootblock-y += ../../../cpu/x86/early_reset.S
+postcar-y += romstage/uart.c
+ramstage-y += romstage/uart.c
+
ramstage-y += acpi.c
ramstage-y += adsp.c
ramstage-y += chip.c
diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c
index a1a29b6..43c62a9 100644
--- a/src/soc/intel/broadwell/romstage/uart.c
+++ b/src/soc/intel/broadwell/romstage/uart.c
@@ -14,13 +14,15 @@
*/
#include <device/pci_def.h>
+#include <console/uart.h>
#include <reg_script.h>
#include <stdint.h>
-#include <uart8250.h>
#include <soc/iobp.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
#include <soc/serialio.h>
-const struct reg_script uart_init[] = {
+const struct reg_script uart_init_script[] = {
/* Set MMIO BAR */
REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE),
/* Enable Memory access and Bus Master */
@@ -41,6 +43,11 @@
REG_SCRIPT_END
};
+uintptr_t uart_platform_base(int idx)
+{
+ return CONFIG_TTYS0_BASE;
+}
+
void pch_uart_init(void)
{
/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
@@ -72,11 +79,11 @@
pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
/* Initialize chipset uart interface */
- reg_script_run_on_dev(dev, uart_init);
+ reg_script_run_on_dev(dev, uart_init_script);
/*
* Perform standard UART initialization
* Divisor 1 is 115200 BAUD
*/
- uart8250_mem_init(CONFIG_TTYS0_BASE, 1);
+ uart_init(0);
}
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index 161c875..50daa3f 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -282,7 +282,8 @@
if (serialio_uart_is_debug(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
- uartmem_setbaseaddr(res->base);
+ printk(BIOS_ERR, "UART base address changed\n");
+ //uartmem_setbaseaddr(res->base);
}
#endif
}
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