Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41215 )
Change subject: mb/google/volteer: Add firmware configuration table ......................................................................
mb/google/volteer: Add firmware configuration table
Add the current firmware configuration table for the volteer mainboard. This is not completely filled out for all fields yet but has the entries needed for audio.
- When I2S options are selected disable the SoundWire GPIOs. - When SoundWire is enabled disable the I2S GPIOs. - When no audio is enabled disable all the GPIOs.
The current mainboard configuration value is read from the Embedded Controller CBI field and provided to the firmware configuration interface for probing.
BUG=b:147462631 TEST=Test that GPIOs are configured as expected based on the current value of the fw_config field in cbi.
Change-Id: I179f8b6436be83a2b37911777764bd26a0d404b7 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Makefile.inc A src/mainboard/google/volteer/fw_config.c 3 files changed, 136 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/41215/1
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index e6c6ec7..3acc0ea 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -13,6 +13,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_LPC + select FW_CONFIG select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc index 9d1bb3f..2ddd508 100644 --- a/src/mainboard/google/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/Makefile.inc @@ -13,6 +13,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
smm-y += smihandler.c
diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c new file mode 100644 index 0000000..64adfe9 --- /dev/null +++ b/src/mainboard/google/volteer/fw_config.c @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __MAINBOARD_FW_CONFIG__ +#define __MAINBOARD_FW_CONFIG__ + +#include <commonlib/helpers.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <fw_config.h> +#include <stdint.h> +#include <soc/gpio.h> + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC_CLK1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC_DATA1 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA0 */ +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), +}; + +static const struct pad_config sndw_enable_pads[] = { + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_CLK */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_DATA */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_DATA */ +}; + +static const struct pad_config sndw_disable_pads[] = { + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SCLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_TXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_RXD */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_RXD */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_TXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SFRM */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_A23, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, DN_20K), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static void audio_db_none_cb(const struct fw_config_option *option) +{ + printk(BIOS_INFO, "%s: Configure GPIOs for no audio.\n", __func__); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); +} + +static void audio_db_i2s_cb(const struct fw_config_option *option) +{ + printk(BIOS_INFO, "%s: Configure GPIOs for I2S audio.\n", __func__); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); +} + +static void audio_db_sndw_cb(const struct fw_config_option *option) +{ + printk(BIOS_INFO, "%s: Configure GPIOs for SoundWire audio.\n", __func__); + gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads)); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); +} + +static const struct fw_config_field volteer_fw_config[] = { + { + FW_CONFIG_FIELD("DB", 0xf, 0), + }, + { + FW_CONFIG_FIELD("THERMAL", 0xf, 4), + }, + { + FW_CONFIG_FIELD("AUDIO", 0x7, 8), + .option = { + FW_CONFIG_OPTION_CB("NONE", 0, audio_db_none_cb), + FW_CONFIG_OPTION_CB("MAX98357_ALC5682I_I2S", 1, audio_db_i2s_cb), + FW_CONFIG_OPTION_CB("MAX98373_ALC5682I_I2S", 2, audio_db_i2s_cb), + FW_CONFIG_OPTION_CB("MAX98373_ALC5682_SNDW", 3, audio_db_sndw_cb) + }, + }, + { + FW_CONFIG_FIELD("TABLETMODE", 0x1, 11), + .option = { + FW_CONFIG_OPTION("DISABLED", 0), + FW_CONFIG_OPTION("ENABLED", 1) + }, + }, + { + FW_CONFIG_FIELD("LTE_DB", 0x3, 12), + .option = { + FW_CONFIG_OPTION("ABSENT", 0), + FW_CONFIG_OPTION("PRESENT", 1) + }, + }, + { } +}; + +size_t mainboard_get_fw_config(const struct fw_config_field **table, uint32_t *config) +{ + if (google_chromeec_cbi_get_fw_config(config) < 0) { + printk(BIOS_ERR, "Could not get fw_config from EC\n"); + return 0; + } + + *table = volteer_fw_config; + return ARRAY_SIZE(volteer_fw_config); +} + +#endif /* __MAINBOARD_FW_CONFIG__ */