Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Subrata Banik, Arthur Heymans, Michael Niewöhner, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35985
to look at the new patch set (#17).
Change subject: intel/skylake: Implement PCIe RP devicetree update based on LCAP ......................................................................
intel/skylake: Implement PCIe RP devicetree update based on LCAP
The old code stumbled when the whole first group of root ports was disabled and also made the (sometimes wrong) assumption that FSP would only hide function 0 if we explicitly told it to disable it. We don't have to make assumptions though, and can read the root-port number from the PCIe link capapilities (LCAP) instead. This is also what we do in ASL code for years already.
This new implementation acts solely on information read from the PCI config space. In a first round, we scan all possible DEVFNs and store which root port has that DEVFN now. Then, we walk through the devicetree that still only knows devices that were originally mentioned in `devicetree.cb`, and update the device paths.
In theory, this should work no matter who (coreboot vs. FSP) reordered the root ports and no matter what rules were used.
Change-Id: Ib17d2b6fd34608603db3936d638bdf5acb46d717 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/include/device/pci_def.h A src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/common/block/pcie/Makefile.inc A src/soc/intel/common/block/pcie/pcie_rp.c M src/soc/intel/skylake/chip.c 5 files changed, 219 insertions(+), 122 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/35985/17