EricR Lai has uploaded this change for review.

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soc/intel/common: Move L1_substates_control to pcie_rp.h

L1_substates_control is common define. Move out of soc level.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I54574b606985e82d00beb1a61cce3097580366a4
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/tigerlake/chip.h
5 files changed, 12 insertions(+), 24 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/49295/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 8e59c9a..f23b9d2 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -7,6 +7,7 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
+#include <intelblocks/pcie_rp.h>
 #include <soc/gpe.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
@@ -136,12 +137,7 @@
 	uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS];
 
 	/* PCIe RP L1 substate */
-	enum L1_substates_control {
-		L1_SS_FSP_DEFAULT,
-		L1_SS_DISABLED,
-		L1_SS_L1_1,
-		L1_SS_L1_2,
-	} PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS];
+	enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS];
 
 	/* PCIe LTR: Enable (1) / Disable (0) */
 	uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS];
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index ca50b13..0115c4b 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -34,4 +34,11 @@
  */
 void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
 
+enum L1_substates_control {
+	L1_SS_FSP_DEFAULT,
+	L1_SS_DISABLED,
+	L1_SS_L1_1,
+	L1_SS_L1_2,
+};
+
 #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 37237bb..49af0d0 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -116,12 +116,7 @@
 	uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
 
 	/* PCIe RP L1 substate */
-	enum L1_substates_control {
-		L1_SS_FSP_DEFAULT,
-		L1_SS_DISABLED,
-		L1_SS_L1_1,
-		L1_SS_L1_2,
-	} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+	enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 
 	/* SMBus */
 	uint8_t SmbusEnable;
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 3b81339..e74d8ce 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -114,12 +114,7 @@
 	uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
 
 	/* PCIe RP L1 substate */
-	enum L1_substates_control {
-		L1_SS_FSP_DEFAULT,
-		L1_SS_DISABLED,
-		L1_SS_L1_1,
-		L1_SS_L1_2,
-	} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+	enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 
 	/* SMBus */
 	uint8_t SmbusEnable;
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index f38330b..29171a5 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -247,12 +247,7 @@
 	uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS];
 
 	/* PCIe RP L1 substate */
-	enum L1_substates_control {
-		L1_SS_FSP_DEFAULT,
-		L1_SS_DISABLED,
-		L1_SS_L1_1,
-		L1_SS_L1_2,
-	} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+	enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 
 	/* PCIe LTR: Enable (1) / Disable (0) */
 	uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];

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