Maulik V Vaghela has uploaded this change for review.
intel/common/pch/gspi: Move gspi functionality to common PCH
GSPI functionality is common for platforms using common base PCH code.
Thus moving this functionality from individual soc to common PCH base.
BUG=none
BRANCH=none
TEST=check if patch builds and KBL, CNL boots with this patch.
Change-Id: I2cf65d56451afac5258c7127854b5fc7f4d84bd1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
---
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/common/pch/Kconfig
A src/soc/intel/common/pch/gspi/Kconfig
A src/soc/intel/common/pch/gspi/Makefile.inc
R src/soc/intel/common/pch/gspi/gspi.c
M src/soc/intel/skylake/Makefile.inc
D src/soc/intel/skylake/gspi.c
7 files changed, 13 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/26728/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index f8f9198..4cce5c3 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -14,7 +14,6 @@
bootblock-y += pmutil.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
-bootblock-y += gspi.c
bootblock-y += i2c.c
bootblock-y += memmap.c
bootblock-y += spi.c
@@ -24,7 +23,6 @@
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
romstage-y += gpio.c
-romstage-y += gspi.c
romstage-y += i2c.c
romstage-y += lpc.c
romstage-y += memmap.c
@@ -39,7 +37,6 @@
ramstage-y += finalize.c
ramstage-y += gpio.c
ramstage-y += graphics.c
-ramstage-y += gspi.c
ramstage-y += gpio.c
ramstage-y += i2c.c
ramstage-y += lockdown.c
@@ -67,7 +64,6 @@
postcar-y += pmutil.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
-verstage-y += gspi.c
verstage-y += i2c.c
verstage-y += pmutil.c
verstage-y += spi.c
diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
index ead0536..9014647 100644
--- a/src/soc/intel/common/pch/Kconfig
+++ b/src/soc/intel/common/pch/Kconfig
@@ -44,5 +44,5 @@
select SOC_INTEL_COMMON_BLOCK_XDCI
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_PCH_LOCKDOWN
-
+ select SOC_INTEL_COMMON_PCH_GSPI
endif
diff --git a/src/soc/intel/common/pch/gspi/Kconfig b/src/soc/intel/common/pch/gspi/Kconfig
new file mode 100644
index 0000000..c07611b
--- /dev/null
+++ b/src/soc/intel/common/pch/gspi/Kconfig
@@ -0,0 +1,5 @@
+config SOC_INTEL_COMMON_PCH_GSPI
+ bool
+ default n
+ help
+ This option allows to have gspi configuration for supported PCH.
diff --git a/src/soc/intel/common/pch/gspi/Makefile.inc b/src/soc/intel/common/pch/gspi/Makefile.inc
new file mode 100644
index 0000000..19ff891
--- /dev/null
+++ b/src/soc/intel/common/pch/gspi/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_PCH_GSPI) += gspi.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_PCH_GSPI) += gspi.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_PCH_GSPI) += gspi.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_GSPI) += gspi.c
+postcar-$(CONFIG_SOC_INTEL_COMMON_PCH_GSPI) += gspi.c
diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/common/pch/gspi/gspi.c
similarity index 92%
rename from src/soc/intel/cannonlake/gspi.c
rename to src/soc/intel/common/pch/gspi/gspi.c
index c5998b5..99fd2b4 100644
--- a/src/soc/intel/cannonlake/gspi.c
+++ b/src/soc/intel/common/pch/gspi/gspi.c
@@ -13,7 +13,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
#include <intelblocks/gspi.h>
#include <soc/pci_devs.h>
@@ -24,8 +23,10 @@
return PCH_DEVFN_GSPI0;
case 1:
return PCH_DEVFN_GSPI1;
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2)
case 2:
return PCH_DEVFN_GSPI2;
+#endif
}
return -1;
}
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 89e48f1..8f673c3 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -15,21 +15,18 @@
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
-bootblock-y += gspi.c
bootblock-y += p2sb.c
bootblock-y += pmutil.c
bootblock-y += spi.c
bootblock-y += lpc.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
-verstage-y += gspi.c
verstage-y += pmutil.c
verstage-y += i2c.c
verstage-y += spi.c
verstage-$(CONFIG_UART_DEBUG) += uart.c
romstage-y += gpio.c
-romstage-y += gspi.c
romstage-y += i2c.c
romstage-y += memmap.c
romstage-y += me.c
@@ -47,7 +44,6 @@
ramstage-y += elog.c
ramstage-y += finalize.c
ramstage-y += gpio.c
-ramstage-y += gspi.c
ramstage-y += i2c.c
ramstage-y += graphics.c
ramstage-y += irq.c
@@ -76,7 +72,6 @@
smm-$(CONFIG_UART_DEBUG) += uart.c
postcar-y += memmap.c
-postcar-y += gspi.c
postcar-y += spi.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c
deleted file mode 100644
index 3fb7c50..0000000
--- a/src/soc/intel/skylake/gspi.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <intelblocks/gspi.h>
-#include <soc/pci_devs.h>
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
- switch (gspi_bus) {
- case 0:
- return PCH_DEVFN_GSPI0;
- case 1:
- return PCH_DEVFN_GSPI1;
- }
- return -1;
-}
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