Patch Set 1:

Patch Set 1:

So if I understand correctly, right now SMRAM on these platforms remains unlocked after coreboot loads the payload?

This are compatible SMRAM region locking not the actual DRAM based SMRAM locking stuff. This register controls below 1 MB VGA region (0xA_0000 till 0xB_FFFF)

Here is the register range that this register protects:

C_BASE_SEG: This field indicates the location of SMM space. Only SMM space between A_0000h and
B_FFFFh is supported, so this field is hardwired to 010b

Ah right, this only locks the CSEG, which we don't typically use here in coreboot, preferring TSEG instead. To "lock" access to TSEG, we program the SMRR registers to prevent access to SMRAM (TSEG region) from any other SAI than SMM_SAI. Is my understanding correct?

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