Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Martin Roth, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Karthikeyan Ramasubramanian, Felix Held.
2 comments:
Commit Message:
Patch Set #1, Line 20: Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Add Reported-by: or Suggested-by: line?
Add requests to abandon related CB:42689, CB:51025, CB:51029 in gerrit?.
File src/soc/amd/common/block/i2c/i2c.c:
/*
* Toggle SCL back and forth 9 times under 100KHz. A single read is
* needed after the writes to force the posted write to complete.
*/
This code was put in place because an i2c device was writing data to SDA, but we stopped clocking mi […]
There is no compulsory HW reset signal for slave device. This 9 dummy clocks is the universally used software reset and it goes way back to the use of DDC in analog VGA cables, early or mid 1990's? Probably had uses even before DDC.
The slave device (an I2C eeprom aka EDID) power cannot be toggled from host (the graphics card) as there is typically a diode arrangement on the EDID part Vcc supply rail for the EDID; the part is to be powerered through video cable to implement Plug'n'Play together with the deeper power-saving modes (DPMS).
This is oftn documented, but I don't remember seeing this in the I2C specification text itself.
https://www.analog.com/media/en/technical-documentation/application-notes/54305147357414AN686_0.pdf
https://espace.cern.ch/CMS-MPA/SiteAssets/SitePages/Documents/I2C_bus_specifications_V2_0.pdf
1.3 Bus clear
http://ww1.microchip.com/downloads/en/DeviceDoc/20006296A.pdf
5.5 Software Reset
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