Furquan Shaikh merged this change.
mb/google/hatch: Create Akemi variant
This is based on the hatch variant
BUG=b:138879565
TEST=FW_NAME="akemi" emerge-hatch coreboot depthcharge intel-cmlfsp
chromeos-bootimage look for image-akemi.*.bin generated under the
/build/hatch/firmware/
Change-Id: I1a868839e2c598f8052d37c99713bc58b21e887c
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/Kconfig.name
A src/mainboard/google/hatch/variants/akemi/Makefile.inc
A src/mainboard/google/hatch/variants/akemi/gpio.c
A src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl
A src/mainboard/google/hatch/variants/akemi/include/variant/ec.h
A src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h
A src/mainboard/google/hatch/variants/akemi/overridetree.cb
8 files changed, 438 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 5991b93..5c7c267 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -71,6 +71,7 @@
config GBB_HWID
string
depends on CHROMEOS
+ default "AKEMI TEST 4326" if BOARD_GOOGLE_AKEMI
default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH
default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS
default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED
@@ -86,6 +87,7 @@
config MAINBOARD_PART_NUMBER
string
+ default "Akemi" if BOARD_GOOGLE_AKEMI
default "Hatch" if BOARD_GOOGLE_HATCH
default "Helios" if BOARD_GOOGLE_HELIOS
default "Kindred" if BOARD_GOOGLE_KINDRED
@@ -109,6 +111,7 @@
config VARIANT_DIR
string
+ default "akemi" if BOARD_GOOGLE_AKEMI
default "hatch" if BOARD_GOOGLE_HATCH
default "helios" if BOARD_GOOGLE_HELIOS
default "kindred" if BOARD_GOOGLE_KINDRED
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name
index 3b5d3f2..e8748e3 100644
--- a/src/mainboard/google/hatch/Kconfig.name
+++ b/src/mainboard/google/hatch/Kconfig.name
@@ -1,5 +1,11 @@
comment "Hatch"
+config BOARD_GOOGLE_AKEMI
+ bool "-> Akemi"
+ select BOARD_GOOGLE_BASEBOARD_HATCH
+ select BOARD_ROMSIZE_KB_16384
+ select SOC_INTEL_COMETLAKE
+
config BOARD_GOOGLE_HATCH
bool "-> Hatch"
select BOARD_GOOGLE_BASEBOARD_HATCH
diff --git a/src/mainboard/google/hatch/variants/akemi/Makefile.inc b/src/mainboard/google/hatch/variants/akemi/Makefile.inc
new file mode 100644
index 0000000..2f590bf
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/akemi/Makefile.inc
@@ -0,0 +1,23 @@
+## This file is part of the coreboot project.
+##
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+SPD_SOURCES = 4G_2400 # 0b000
+SPD_SOURCES += empty_ddr4 # 0b001
+SPD_SOURCES += 8G_2400 # 0b010
+SPD_SOURCES += 8G_2666 # 0b011
+SPD_SOURCES += 16G_2400 # 0b100
+SPD_SOURCES += 16G_2666 # 0b101
+
+bootblock-y += gpio.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c
new file mode 100644
index 0000000..5a58839
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/akemi/gpio.c
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <console/console.h>
+
+static const struct pad_config gpio_table[] = {
+ /* A0 : NC */
+ PAD_NC(GPP_A0, NONE),
+ /* A6 : NC */
+ PAD_NC(GPP_A6, NONE),
+ /* A8 : NC */
+ PAD_NC(GPP_A8, NONE),
+ /* A10 : NC */
+ PAD_NC(GPP_A10, NONE),
+ /* A11 : NC */
+ PAD_NC(GPP_A11, NONE),
+ /* A12 : NC */
+ PAD_NC(GPP_A12, NONE),
+ /* A18 : NC */
+ PAD_NC(GPP_A18, NONE),
+ /* A19 : NC */
+ PAD_NC(GPP_A19, NONE),
+ /* A22 : NC */
+ PAD_NC(GPP_A22, NONE),
+ /* A23 : NC */
+ PAD_NC(GPP_A23, NONE),
+ /* B20 : NC */
+ PAD_NC(GPP_B20, NONE),
+ /* B21 : NC */
+ PAD_NC(GPP_B21, NONE),
+ /* B22 : NC */
+ PAD_NC(GPP_B22, NONE),
+ /* C11 : NC */
+ PAD_NC(GPP_C11, NONE),
+ /* C15 : NC */
+ PAD_NC(GPP_C15, NONE),
+ /* F1 : NC */
+ PAD_NC(GPP_F1, NONE),
+ /* F3 : MEM_STRAP_3 */
+ PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
+ /* F10 : MEM_STRAP_2 */
+ PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
+ /* F11 : EMMC_CMD ==> EMMC_CMD */
+ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+ /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+ /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+ /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */
+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+ /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+ /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+ /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */
+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+ /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */
+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+ /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+ /* F20 : EMMC_RCLK ==> EMMC_RCLK */
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+ /* F21 : EMMC_CLK ==> EMMC_CLK */
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+ /* F22 : EMMC_RESET# ==> EMMC_RST_L */
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+ /* H6 : NC */
+ PAD_NC(GPP_H6, NONE),
+ /* H7 : NC */
+ PAD_NC(GPP_H7, NONE),
+ /* H19 : MEM_STRAP_0 */
+ PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
+ /* H22 : MEM_STRAP_1 */
+ PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
+};
+
+const struct pad_config *override_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/*
+ * GPIOs configured before ramstage
+ * Note: the Hatch platform's romstage will configure
+ * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
+ * as inputs before it reads them, so they are not
+ * needed in this table.
+ */
+static const struct pad_config early_gpio_table[] = {
+ /* A12 : NC */
+ PAD_NC(GPP_A12, NONE),
+ /* B15 : H1_SLAVE_SPI_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* B16 : H1_SLAVE_SPI_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* B17 : H1_SLAVE_SPI_MISO_R */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* B18 : H1_SLAVE_SPI_MOSI_R */
+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* C14 : BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_C14, 0, DEEP),
+ /* PCH_WP_OD */
+ PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+ /* C21 : H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+ /* C23 : WLAN_PE_RST# */
+ PAD_CFG_GPO(GPP_C23, 1, DEEP),
+ /* E1 : M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+ /* E5 : SATA_DEVSLP1 */
+ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
+ /* F2 : MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
+ /* F11 : EMMC_CMD ==> EMMC_CMD */
+ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+ /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+ /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+ /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */
+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+ /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+ /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+ /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */
+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+ /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */
+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+ /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+ /* F20 : EMMC_RCLK ==> EMMC_RCLK */
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+ /* F21 : EMMC_CLK ==> EMMC_CLK */
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+ /* F22 : EMMC_RESET# ==> EMMC_RST_L */
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..31f72b3
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h b/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h
new file mode 100644
index 0000000..768987d
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/akemi/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h
new file mode 100644
index 0000000..b257589
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_H19
+#define GPIO_MEM_CONFIG_1 GPP_H22
+#define GPIO_MEM_CONFIG_2 GPP_F10
+#define GPIO_MEM_CONFIG_3 GPP_F3
+
+#endif
diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb
new file mode 100644
index 0000000..88d33e7
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb
@@ -0,0 +1,181 @@
+chip soc/intel/cannonlake
+
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ [PchSerialIoIndexSPI0] = PchSerialIoPci,
+ [PchSerialIoIndexSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| GSPI1 | FP MCU |
+ #| I2C0 | Touchpad |
+ #| I2C1 | Touch screen |
+ #| I2C4 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 60,
+ .fall_time_ns = 25,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 150,
+ .fall_time_ns = 150,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 120,
+ .fall_time_ns = 120,
+ },
+ }"
+
+ # GPIO for SD card detect
+ register "sdcard_cd_gpio" = "vSD3_CD_B"
+
+ # Enable eMMC HS400
+ register "ScsEmmcHs400Enabled" = "1"
+
+ device domain 0 on
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)"
+ register "wake" = "GPE0_DW0_21"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""PNP0C50""
+ register "generic.desc" = ""Synaptics Touchpad""
+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)"
+ register "generic.wake" = "GPE0_DW0_21"
+ register "generic.probed" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 0x2c on end
+ end
+ end # I2C #0
+ device pci 15.1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+ register "probed" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+ register "reset_delay_ms" = "100"
+ register "reset_off_delay_ms" = "5"
+ register "has_power_resource" = "1"
+ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+ register "stop_off_delay_ms" = "5"
+ device i2c 10 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""GDIX0000""
+ register "generic.desc" = ""Goodix Touchscreen""
+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+ register "generic.reset_delay_ms" = "10"
+ register "generic.reset_off_delay_ms" = "1"
+ register "generic.has_power_resource" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 5d on end
+ end
+ chip drivers/generic/gpio_keys
+ register "name" = ""PENH""
+ register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)"
+ register "key.wake" = "GPE0_DW0_08"
+ register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
+ register "key.dev_name" = ""EJCT""
+ register "key.linux_code" = "SW_PEN_INSERTED"
+ register "key.linux_input_type" = "EV_SW"
+ register "key.label" = ""pen_eject""
+ device generic 0 on end
+ end
+ end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 on
+ chip drivers/i2c/sx9310
+ register "desc" = ""SAR Proximity Sensor""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)"
+ register "speed" = "I2C_SPEED_FAST"
+ register "uid" = "1"
+ register "reg_prox_ctrl0" = "0x10"
+ register "reg_prox_ctrl1" = "0x00"
+ register "reg_prox_ctrl2" = "0x84"
+ register "reg_prox_ctrl3" = "0x0e"
+ register "reg_prox_ctrl4" = "0x07"
+ register "reg_prox_ctrl5" = "0xc6"
+ register "reg_prox_ctrl6" = "0x20"
+ register "reg_prox_ctrl7" = "0x0d"
+ register "reg_prox_ctrl8" = "0x8d"
+ register "reg_prox_ctrl9" = "0x43"
+ register "reg_prox_ctrl10" = "0x1f"
+ register "reg_prox_ctrl11" = "0x00"
+ register "reg_prox_ctrl12" = "0x00"
+ register "reg_prox_ctrl13" = "0x00"
+ register "reg_prox_ctrl14" = "0x00"
+ register "reg_prox_ctrl15" = "0x00"
+ register "reg_prox_ctrl16" = "0x00"
+ register "reg_prox_ctrl17" = "0x00"
+ register "reg_prox_ctrl18" = "0x00"
+ register "reg_prox_ctrl19" = "0x00"
+ register "reg_sar_ctrl0" = "0x50"
+ register "reg_sar_ctrl1" = "0x8a"
+ register "reg_sar_ctrl2" = "0x3c"
+ device i2c 28 on end
+ end
+ end # I2C #3
+ device pci 19.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5682""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
+ register "property_count" = "1"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ end #I2C #4
+ device pci 1a.0 on end # eMMC
+ device pci 1e.3 on
+ chip drivers/spi/acpi
+ register "name" = ""CRFP""
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "uid" = "1"
+ register "compat_string" = ""google,cros-ec-spi""
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
+ device spi 1 on end
+ end # FPMCU
+ end # GSPI #1
+ end
+
+end
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