Attention is currently required from: Furquan Shaikh, Julius Werner, Angel Pons, Karthik Ramasubramanian.

Raul Rangel uploaded patch set #8 to this change.

View Change

commonlib/mem_pool: Allow configuring the alignment

AMD platforms require the destination to be 64 byte aligned in order to
use the SPI DMA controller. This is enforced by the destination address
register because the first 6 bits are marked as reserved.

This change adds an option to the mem_pool so the alignment can be
configured.

BUG=b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075
---
M src/commonlib/include/commonlib/mem_pool.h
M src/commonlib/mem_pool.c
M src/lib/cbfs.c
3 files changed, 16 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/56580/8

To view, visit change 56580. To unsubscribe, or for help writing mail filters, visit settings.