Attention is currently required from: Jason Nien, Karthik Ramasubramanian, Mark Hasemeyer, Martin L Roth.

Mark Hasemeyer uploaded patch set #4 to this change.

View Change

mb/google/guybrush: Set PS2K_IRQ to level/low

On guybrush, keyboard presses are signaled by the EC via eSPI virtual
wire. The interrupt is shared with others and should be active low.

From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"):
> The default state for the IRQ lines when the eSPI controller comes
> out of reset is high. This is because the IRQ lines are shared with
> the other IRQ sources using AND gates. This means that in order to
> not cause any spurious interrupts or miss any interrupts, the
> IO-APIC must use a low polarity trigger.

Setting `vw_irq_polarity` in the device tree provides an option to
invert interrupts from the eSPI controller, but the register is
initialized from verstage which is baked into RO.

As a workaround, the necessary interrupts on the EC have been
reconfigured to be active low, and we can modify the IO-APIC
accordingly.

EC related CL here: https://crrev.com/c/4891663

BUG=b:218874489
TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage`
     -Flash new RW fw and verify keyboard is functional
     -`suspend_stress_test -c 1` and verify i8042 irq is removed as a
     wake source
     -`echo mem > /sys/power/state`. Press key and verify system wake
     from i8042.

Cq-Depend: chromium:4891663
Change-Id: I7d093d94a666263684645ef724e945069c68c806
Signed-off-by: Mark Hasemeyer <markhas@google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
2 files changed, 5 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/78137/4

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