Aamir Bohra uploaded patch set #3 to this change.

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soc/intel/{cannonlake,skylake}: Take ITSS polarity snaphot after GPIO configuration

This implementation moves saving  ITSS IPCx regsister snaphsot after
the GPIO pad configuration has configured the polarity bits for active
low interrupts.

BUG=b:123315212
TEST=Verify the ITSS polarities set in ITSS IPCx registers are correctly
     restored for active low interrupts ater FSP-S call.

Change-Id: Id7b6f732759538ca41c872308727b1d87c2c5d85
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/skylake/chip_fsp20.c
3 files changed, 14 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31246/3

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