Felix Singer has uploaded this change for review.
[RFC] treewide: Configure PCI Bus Master based on config option
Change-Id: I25565315a5ddf8d53097ac4cb4884ecebcc9c0a9
Signed-off-by: Felix Singer <felix.singer@secunet.com>
---
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/ironlake/early_init.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/stoneyridge/psp.c
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/broadwell/adsp.c
M src/soc/intel/broadwell/hda.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/gspi/gspi.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/scs/early_mmc.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/denverton_ns/bootblock/uart.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/xhci.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/hdaudio.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/hdaudio.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
65 files changed, 101 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/42460/1
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 3d48ca2..af21802 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -157,7 +157,7 @@
mmio = res2mmio(gtt_res, 0, 0);
if (!CONFIG(NO_GFX_INIT))
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
/* PCI Init, will run VBIOS */
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 68072ff..8320f59 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -468,7 +468,7 @@
gma_setup_panel(dev);
if (!CONFIG(NO_GFX_INIT))
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index c6b5a12..64a843e 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -59,7 +59,7 @@
printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */
- pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* Mini-HD configuration */
reg32 = read32(base + 0x100c);
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 929968e..f677d50 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -671,7 +671,7 @@
;
if (!CONFIG(NO_GFX_INIT))
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
@@ -711,7 +711,7 @@
u8 val;
if (!CONFIG(NO_GFX_INIT))
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
if (get_option(&val, "tft_brightness") == CB_SUCCESS)
pci_write_config8(dev, 0xf4, val);
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c
index b6c5f0f..908ff8d 100644
--- a/src/northbridge/intel/ironlake/early_init.c
+++ b/src/northbridge/intel/ironlake/early_init.c
@@ -132,8 +132,8 @@
early_cpu_init();
pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR);
- pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
/* Magic for S3 resume. Must be done early. */
if (s3_resume) {
diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c
index 8baccb2..9fabe74 100644
--- a/src/northbridge/intel/ironlake/gma.c
+++ b/src/northbridge/intel/ironlake/gma.c
@@ -138,7 +138,7 @@
intel_gma_init_igd_opregion();
if (!CONFIG(NO_GFX_INIT))
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!gtt_res || !gtt_res->base)
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index e46bd7c..12a1b7c 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -221,7 +221,7 @@
intel_gma_init_igd_opregion();
if (!CONFIG(NO_GFX_INIT))
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
/* PCI init, will run VBIOS */
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 83a0279..fbf25b3 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -591,7 +591,7 @@
gma_pm_init_pre_vbios(dev);
if (!CONFIG(NO_GFX_INIT))
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
if (!CONFIG(MAINBOARD_USE_LIBGFXINIT))
/* PCI Init, will run VBIOS */
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index 68d382e..1e77b4b 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -25,7 +25,7 @@
intel_gma_init_igd_opregion();
if (!CONFIG(NO_GFX_INIT))
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* configure GMBUSFREQ */
pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc);
diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c
index c24b8be..f7bed62 100644
--- a/src/soc/amd/stoneyridge/psp.c
+++ b/src/soc/amd/stoneyridge/psp.c
@@ -26,8 +26,9 @@
/* Enable memory access and master */
cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND);
- cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ cmd |= PCI_COMMAND_MEMORY;
pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd);
+ pci_configure_bus_master(dev);
};
void *soc_get_mbox_address(void)
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 2137e49..828d0b7 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -68,8 +68,8 @@
pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */
pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS);
pci_write_config16(pmc, PCI_COMMAND,
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER);
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
}
void bootblock_soc_early_init(void)
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 094e1c2..d66d543 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -267,7 +267,8 @@
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SPECIAL);
+ pci_configure_bus_master(dev);
/* Use IRQ9 for SCI Interrupt */
write32((void *)(ilb_base + ACTL), 0);
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index b8699a2..dcff272 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -23,7 +23,8 @@
u32 tmp32;
/* Ensure memory and bus master are enabled */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
/* Find BAR0 and BAR1 */
bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c
index 1640825..569dc26 100644
--- a/src/soc/intel/broadwell/hda.c
+++ b/src/soc/intel/broadwell/hda.c
@@ -93,7 +93,7 @@
printk(BIOS_DEBUG, "HDA: base = %p\n", base);
/* Set Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
hda_pch_init(dev, base);
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 41167b1..6a81f53 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -501,7 +501,7 @@
return;
if (!CONFIG(NO_GFX_INIT))
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* Wait for any configured pre-graphics delay */
if (!acpi_is_wakeup_s3()) {
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 7449902..c903605 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -721,7 +721,8 @@
mei_base_address = res2mmio(res, 0, 0);
/* Ensure Memory and Bus Master bits are set */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
/* Clean up status for next message */
read_host_csr(&host);
diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c
index b91d73d..725e9dc 100644
--- a/src/soc/intel/broadwell/minihd.c
+++ b/src/soc/intel/broadwell/minihd.c
@@ -61,7 +61,7 @@
printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* Mini-HD configuration */
reg32 = read32(base + 0x100c);
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 9eb14d9..9271fe1 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -580,7 +580,7 @@
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
/* Enable Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* Set Cache Line Size to 0x10 */
pci_write_config8(dev, 0x0c, 0x10);
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index 20a5d9a..cd33d55 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -163,7 +163,8 @@
printk(BIOS_DEBUG, "Initializing Serial IO device\n");
/* Ensure memory and bus master are enabled */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
/* Find BAR0 and BAR1 */
bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index fecc71e..5c355a5 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -95,7 +95,8 @@
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
/* Enable Bus Master and MMIO Space */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
cse.sec_bar = tempbar;
}
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 655d113..e741892 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -272,7 +272,8 @@
spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY);
/* Enable Bus Master and MMIO Space */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Initialize SPI to allow BIOS to write/erase on flash. */
fast_spi_init();
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index f232ee5..8e3b1a3 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -55,7 +55,7 @@
return;
if (!CONFIG(NO_GFX_INIT))
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
if (!acpi_is_wakeup_s3() && display_init_required()) {
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 599ab7e..65bd287 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -172,8 +172,8 @@
static void gspi_set_base_addr(int devfn, struct device *dev, uintptr_t base)
{
pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
- pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER);
+ pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
}
#endif
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index f7c241d..8931731 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -68,8 +68,9 @@
/* Prepare early base address for access before memory */
base = dw_i2c_get_soc_early_base(bus);
pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
- pci_write_config16(dev, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+ pci_configure_bus_master(dev);
/* Take device out of reset */
lpss_reset_release(base);
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 4f4ab43..128be7a 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -22,8 +22,8 @@
pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0);
/* Enable P2SB MSE */
- pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND,
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
}
/*
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index f36366a..b06f86c 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -19,7 +19,7 @@
pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
/* Enable Bus Master */
- pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* Set Cache Line Size to 0x10 */
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c
index caee7d9..69d035d 100644
--- a/src/soc/intel/common/block/scs/early_mmc.c
+++ b/src/soc/intel/common/block/scs/early_mmc.c
@@ -31,8 +31,9 @@
{
pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0,
PRERAM_MMC_BASE_ADDRESS);
- pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND,
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+ pci_configure_bus_master(dev);
}
static void disable_mmc_controller_bar(void)
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index cc5e485..9a8eb1d 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -14,7 +14,7 @@
#include <soc/iomap.h>
#include <soc/nvs.h>
-#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)
+#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY)
#define UART_CONSOLE_INVALID_INDEX 0xFF
extern const struct uart_gpio_pad_config uart_gpio_pads[];
@@ -68,6 +68,7 @@
/* Enable memory access and bus master */
pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE);
+ pci_configure_bus_master(dev);
uart_lpss_init(device, baseaddr);
}
diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c
index 7514fee..e8b8c7a 100644
--- a/src/soc/intel/denverton_ns/bootblock/uart.c
+++ b/src/soc/intel/denverton_ns/bootblock/uart.c
@@ -42,7 +42,8 @@
#if (CONFIG(NON_LEGACY_UART_MODE))
PCI_COMMAND_MEMORY |
#endif
- PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+ PCI_COMMAND_IO);
+ pci_configure_bus_master(dev);
#if (CONFIG(CONSOLE_SERIAL_230400))
/* Change the highest speed to 230400 */
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
index 05c6484..8918c2d 100644
--- a/src/soc/intel/denverton_ns/lpc.c
+++ b/src/soc/intel/denverton_ns/lpc.c
@@ -452,8 +452,9 @@
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
- PCI_COMMAND_SPECIAL | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ PCI_COMMAND_SPECIAL | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_IO);
+ pci_configure_bus_master(dev);
/* Serial IRQ initialization. */
pch_enable_serial_irqs(dev);
diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c
index 25a0e59..92dbf59 100644
--- a/src/soc/intel/denverton_ns/pmc.c
+++ b/src/soc/intel/denverton_ns/pmc.c
@@ -40,9 +40,9 @@
pwrm_base = pci_read_config32(dev, PMC_PWRM_BASE) & MASK_PMC_PWRM_BASE;
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_IO);
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
+ PCI_COMMAND_IO);
+ pci_configure_bus_master(dev);
/* Setup power options. */
pch_power_options(dev);
diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c
index d631117..0797cc3 100644
--- a/src/soc/intel/denverton_ns/sata.c
+++ b/src/soc/intel/denverton_ns/sata.c
@@ -23,9 +23,9 @@
/* SATA configuration is handled by the FSP */
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_IO);
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
+ PCI_COMMAND_IO);
+ pci_configure_bus_master(dev);
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c
index abdeb60..a6874ff 100644
--- a/src/soc/intel/denverton_ns/xhci.c
+++ b/src/soc/intel/denverton_ns/xhci.c
@@ -16,8 +16,8 @@
printk(BIOS_NOTICE, "pch: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND,
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
}
static struct device_operations usb_xhci_ops = {
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 43a88b7..4191a1a 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -97,8 +97,7 @@
write32(bar5 + HOST_CTL, val | HOST_CTL_AHCI_EN);
}
- dev->command |= PCI_COMMAND_MASTER;
- pci_write_config8(dev, PCI_COMMAND, dev->command);
+ pci_configure_bus_master(dev);
printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n");
}
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 4f5d8ca..530a896 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -261,7 +261,7 @@
}
/* Set Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
pci_write_config8(dev, 0x3c, 0x0a); // unused?
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 40b0cc2b..fd5f7d8 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -564,7 +564,8 @@
mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
/* Clean up status for next message */
read_host_csr(&host);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index e65b8e5..f03e91b 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -550,7 +550,8 @@
mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
/* Clean up status for next message */
read_host_csr(&host);
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index 895135b..2c90581 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -14,7 +14,7 @@
printk(BIOS_DEBUG, "PCI init.\n");
/* Enable Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* This device has no interrupt */
pci_write_config8(dev, INTR, 0xff);
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index c381d33..663fc08 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -210,7 +210,7 @@
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
/* Enable Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 8bc45f6..496892a 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -30,7 +30,7 @@
pci_write_config32(dev, 0xfc, 0x205b1708);
#endif
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
//pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
/* For others, done in MRC. */
diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c
index 2abfa8a..1c62372 100644
--- a/src/southbridge/intel/i82801dx/usb.c
+++ b/src/southbridge/intel/i82801dx/usb.c
@@ -11,7 +11,8 @@
{
printk(BIOS_DEBUG, "USB: Setting up controller.. ");
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
+ PCI_COMMAND_INVALIDATE);
+ pci_configure_bus_master(dev);
printk(BIOS_DEBUG, "done.\n");
}
diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c
index e333bb6..508c1ee 100644
--- a/src/southbridge/intel/i82801dx/usb2.c
+++ b/src/southbridge/intel/i82801dx/usb2.c
@@ -12,7 +12,8 @@
{
printk(BIOS_DEBUG, "USB: Setting up controller.. ");
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
+ PCI_COMMAND_INVALIDATE);
+ pci_configure_bus_master(dev);
printk(BIOS_DEBUG, "done.\n");
}
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index 205fb0d..af0b0f2 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -229,7 +229,7 @@
pci_write_config32(dev, 0x120, reg32);
/* Set Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
pci_write_config8(dev, 0x3c, 0x0a); // unused?
diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c
index 7fb489d..93d7177 100644
--- a/src/southbridge/intel/i82801gx/ide.c
+++ b/src/southbridge/intel/i82801gx/ide.c
@@ -29,7 +29,8 @@
enable_secondary = config->ide_enable_secondary;
}
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+ pci_configure_bus_master(dev);
/* Native Capable, but not enabled. */
pci_write_config8(dev, 0x09, 0x8a);
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index 7472438..363bfa6 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -13,9 +13,7 @@
u8 reg8;
/* Enable Bus Master */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ pci_configure_bus_master(dev);
/* This device has no interrupt */
pci_write_config8(dev, INTR, 0xff);
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index adf0e49..b3223b4 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -46,7 +46,7 @@
printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
/* Enable Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it
diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c
index 8ce57df..791ae1d 100644
--- a/src/southbridge/intel/i82801gx/usb.c
+++ b/src/southbridge/intel/i82801gx/usb.c
@@ -14,7 +14,7 @@
/* USB Specification says the device must be Bus Master */
printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
// Erratum
pci_write_config8(dev, 0xca, 0x00);
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index f665ab7..fe581e1 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -17,7 +17,8 @@
u8 reg8;
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
+ pci_configure_bus_master(dev);
reg32 = pci_read_config32(dev, 0xdc);
reg32 |= (1 << 31) | (1 << 27);
diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c
index 6f82cb4..487507e 100644
--- a/src/southbridge/intel/i82801ix/hdaudio.c
+++ b/src/southbridge/intel/i82801ix/hdaudio.c
@@ -229,7 +229,7 @@
pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */
/* Set Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
// Docking not supported
pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index a8e7b11..6b07d8a 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -17,7 +17,7 @@
printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n");
/* Enable Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index cac0375..0621fdc 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -166,9 +166,9 @@
*/
pci_write_config16(dev, PCI_COMMAND,
- PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | /* read-only in IDE modes */
PCI_COMMAND_IO);
+ pci_configure_bus_master(dev);
if (sata_mode != 0)
/* No AHCI: clear AHCI base */
pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c
index 64f23f6..6297f0e 100644
--- a/src/southbridge/intel/i82801ix/usb_ehci.c
+++ b/src/southbridge/intel/i82801ix/usb_ehci.c
@@ -11,7 +11,7 @@
static void usb_ehci_init(struct device *dev)
{
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
printk(BIOS_DEBUG, "done.\n");
}
diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c
index 4ba7828..68c3023 100644
--- a/src/southbridge/intel/i82801jx/hdaudio.c
+++ b/src/southbridge/intel/i82801jx/hdaudio.c
@@ -229,7 +229,7 @@
pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */
/* Set Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
// Docking not supported
pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c
index 5195522..23649a1 100644
--- a/src/southbridge/intel/i82801jx/pcie.c
+++ b/src/southbridge/intel/i82801jx/pcie.c
@@ -17,7 +17,7 @@
printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n");
/* Enable Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it
diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c
index 73a7d82..2bf6809 100644
--- a/src/southbridge/intel/i82801jx/sata.c
+++ b/src/southbridge/intel/i82801jx/sata.c
@@ -160,9 +160,9 @@
*/
pci_write_config16(dev, PCI_COMMAND,
- PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | /* read-only in IDE modes */
PCI_COMMAND_IO);
+ pci_configure_bus_master(dev);
if (sata_mode != 0)
/* No AHCI: clear AHCI base */
pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c
index 893bb29..51c71a7 100644
--- a/src/southbridge/intel/i82801jx/usb_ehci.c
+++ b/src/southbridge/intel/i82801jx/usb_ehci.c
@@ -11,7 +11,7 @@
static void usb_ehci_init(struct device *dev)
{
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
printk(BIOS_DEBUG, "done.\n");
}
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index 4763703..f544c73 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -13,9 +13,9 @@
static void p64h2_ioapic_enable(struct device *dev)
{
/* We have to enable MEM and Bus Master for IOAPIC */
- uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-
+ uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, command);
+ pci_configure_bus_master(dev);
}
/**
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 59a384a..5a7a8cf 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -261,7 +261,7 @@
pci_write_config32(dev, 0xd0, reg32);
/* Set Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
pci_write_config8(dev, 0x3c, 0x0a); // unused?
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 2c9c87c..f413ec3 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -487,8 +487,9 @@
/* Ensure Memory and Bus Master bits are set */
reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ reg16 |= PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
+ pci_configure_bus_master(dev);
/* Clean up status for next message */
read_host_csr(&host);
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 7ad9929..1be011e 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -29,7 +29,7 @@
pci_write_config32(dev, 0xf4, 0x00808588);
pci_write_config32(dev, 0xfc, 0x301b1728);
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
access_cntl = pci_read_config8(dev, 0x80);
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index f415170..0410cf5 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -125,7 +125,7 @@
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
/* Set Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
azalia_pch_init(dev, base);
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index aeab0c7..45f9c71 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -735,7 +735,8 @@
mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
/* Clean up status for next message */
read_host_csr(&host);
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index d957e8d..f7308a5 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -659,7 +659,7 @@
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
/* Enable Bus Master */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+ pci_configure_bus_master(dev);
/* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index cdb1f35..03584c2 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -137,7 +137,8 @@
printk(BIOS_DEBUG, "Initializing Serial IO device\n");
/* Ensure memory and bus master are enabled */
- pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
/* Find BAR0 and BAR1 */
bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index 52b3ed8..02ad4c0 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -72,7 +72,8 @@
/* Make sure memory space is enabled */
pci_write_config16(dev, PCI_COMMAND, pci_cmd |
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ PCI_COMMAND_MEMORY);
+ pci_configure_bus_master(dev);
}
/*
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