Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22288
Change subject: src/soc/amd/stoneyridge: Replace AMD types with coreboot types. ......................................................................
src/soc/amd/stoneyridge: Replace AMD types with coreboot types.
AMD uses u8, u16 and u32 types, while coreboot comunity uses uint8_t, uint16_t and uint32_t. Replace the types in southbridge.h function prototypes and the actual functions declared by these prototypes.
BUG=b:68007655
Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/early_setup.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c 3 files changed, 39 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/22288/1
diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index ecae7ab..fc61c6b 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -33,7 +33,7 @@
void configure_stoneyridge_uart(void) { - u8 byte, byte2; + uint8_t byte, byte2;
if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) return; @@ -71,7 +71,7 @@
void sb_pci_port80(void) { - u8 byte; + uint8_t byte; pci_devfn_t dev;
dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); @@ -83,7 +83,7 @@
void sb_lpc_port80(void) { - u8 byte; + uint8_t byte; pci_devfn_t dev;
/* Enable LPC controller */ @@ -103,7 +103,7 @@ void sb_lpc_decode(void) { pci_devfn_t dev; - u32 tmp = 0; + uint32_t tmp = 0;
/* Enable I/O decode to LPC bus */ dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); @@ -170,7 +170,7 @@ static void lpc_wideio_window(uint16_t base, uint16_t size) { pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - u32 tmp; + uint32_t tmp;
/* Support 512 or 16 bytes per range */ assert(size == 512 || size == 16); @@ -210,7 +210,7 @@ lpc_wideio_window(base, 16); }
-int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +int s3_save_nvram_early(uint32_t dword, int size, int nvram_pos) { int i; printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", @@ -225,9 +225,9 @@ return nvram_pos; }
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +int s3_load_nvram_early(int size, uint32_t *old_dword, int nvram_pos) { - u32 data = *old_dword; + uint32_t data = *old_dword; int i; for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); @@ -243,7 +243,7 @@
void sb_clk_output_48Mhz(void) { - u32 ctrl; + uint32_t ctrl;
/* * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so @@ -260,7 +260,7 @@ { /* Make sure the base address is predictable */ device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - u32 base, enables; + uint32_t base, enables;
base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); enables = base & 0xf; @@ -275,7 +275,7 @@ return (uintptr_t)base; }
-void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) +void sb_set_spi100(uint16_t norm, uint16_t fast, uint16_t alt, uint16_t tpm) { uintptr_t base = sb_spibase(); write16((void *)base + SPI100_SPEED_CONFIG, @@ -294,7 +294,7 @@ & ~SPI_RD4DW_EN_HOST); }
-void sb_set_readspeed(u16 norm, u16 fast) +void sb_set_readspeed(uint16_t norm, uint16_t fast) { uintptr_t base = sb_spibase(); write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) @@ -303,7 +303,7 @@ | (fast << SPI_FAST_SPEED_SH)); }
-void sb_read_mode(u32 mode) +void sb_read_mode(uint32_t mode) { uintptr_t base = sb_spibase(); write32((void *)base + SPI_CNTRL0, @@ -315,7 +315,7 @@ { device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); /* LPC device */
- u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); + uint32_t spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase | ROUTE_TPM_2_SPI); } @@ -331,7 +331,7 @@ */ void sb_enable_rom(void) { - u8 reg8; + uint8_t reg8; pci_devfn_t dev;
dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 55ded9f..5302bc0 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify @@ -264,28 +264,28 @@ void sb_lpc_port80(void); void sb_lpc_decode(void); void sb_pci_port80(void); -void sb_read_mode(u32 mode); -void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void sb_set_readspeed(u16 norm, u16 fast); +void sb_read_mode(uint32_t mode); +void sb_set_spi100(uint16_t norm, uint16_t fast, uint16_t alt, uint16_t tpm); +void sb_set_readspeed(uint16_t norm, uint16_t fast); void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); -u8 pm_read8(u8 reg); -u16 pm_read16(u8 reg); -u32 pm_read32(u8 reg); -void pm_write8(u8 reg, u8 value); -void pm_write16(u8 reg, u16 value); -void pm_write32(u8 reg, u32 value); -u8 smi_read8(u8 reg); -u16 smi_read16(u8 reg); -u32 smi_read32(u8 reg); -void smi_write8(u8 reg, u8 value); -void smi_write16(u8 reg, u16 value); -void smi_write32(u8 reg, u32 value); +uint8_t pm_read8(uint8_t reg); +uint16_t pm_read16(uint8_t reg); +uint32_t pm_read32(uint8_t reg); +void pm_write8(uint8_t reg, uint8_t value); +void pm_write16(uint8_t reg, uint16_t value); +void pm_write32(uint8_t reg, uint32_t value); +uint8_t smi_read8(uint8_t reg); +uint16_t smi_read16(uint8_t reg); +uint32_t smi_read32(uint8_t reg); +void smi_write8(uint8_t reg, uint8_t value); +void smi_write16(uint8_t reg, uint16_t value); +void smi_write32(uint8_t reg, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); +int s3_load_nvram_early(int size, uint32_t *old_dword, int nvram_pos); void s3_resume_init_data(void *FchParams); -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +int s3_save_nvram_early(uint32_t dword, int size, int nvram_pos); void bootblock_fch_early_init(void);
#endif /* __STONEYRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index ebf791d..707e9bd 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -15,32 +15,32 @@
#include <soc/southbridge.h>
-void pm_write8(u8 reg, u8 value) +void pm_write8(uint8_t reg, uint8_t value) { write8((void *)(PM_MMIO_BASE + reg), value); }
-u8 pm_read8(u8 reg) +uint8_t pm_read8(uint8_t reg) { return read8((void *)(PM_MMIO_BASE + reg)); }
-void pm_write16(u8 reg, u16 value) +void pm_write16(uint8_t reg, uint16_t value) { write16((void *)(PM_MMIO_BASE + reg), value); }
-u16 pm_read16(u8 reg) +uint16_t pm_read16(uint8_t reg) { return read16((void *)(PM_MMIO_BASE + reg)); }
-void pm_write32(u8 reg, u32 value) +void pm_write32(uint8_t reg, uint32_t value) { write32((void *)(PM_MMIO_BASE + reg), value); }
-u32 pm_read32(u8 reg) +uint32_t pm_read32(uint8_t reg) { return read32((void *)(PM_MMIO_BASE + reg)); }