Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Kapil Porwal, Angel Pons, Eric Lai.

Subrata Banik uploaded patch set #2 to this change.

View Change

soc/intel/meteorlake: Refactor bootblock SoC programming code

This patch ensures the IP initialization being done as part of MTL
bootblock code is able to complete the bootblock phase without any
visible hang.

The re-ordering in the MTL bootblock SoC programming is required to
ensure the SA early initialization is taking place prior to
performing any PCI Read/Write operation (like P2SB bar enabling for
IOE die etc.).

Additionally, Fast SPI init takes place prior to enabling ROM caching
etc.

BUG=b:224325352
TEST= Able to build and start booting the MTL simics.
Without this change, the code execution is stuck as below:

[NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz
[DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG]  CPU: AES supported, TXT supported, VT supported
[DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG]  IGD: device id ffff (rev ff) is Unknown
[INFO ]  PMC: Using default GPE route.
[INFO ]  VBNV: CMOS invalid, restoring from flash
[ERROR]  init_vbnv: failed to locate NVRAM
[EMERG]  Cannot locate primary CBFS

Able to detect the Flash and reading the SPI flash layout in proper
with this change as below:
[NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz
[DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG]  CPU: AES supported, TXT supported, VT supported
[DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG]  IGD: device id ffff (rev ff) is Unknown
[INFO ]  PMC: Using default GPE route.
[INFO ]  VBNV: CMOS invalid, restoring from flash
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1804000.
[DEBUG]  FMAP: base = 0x0 size = 0x2000000 #areas = 33
[DEBUG]  FMAP: area RW_NVRAM found @ 112b000 (24576 bytes)
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x2000000

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a
---
M src/soc/intel/meteorlake/bootblock/bootblock.c
M src/soc/intel/meteorlake/bootblock/soc_die.c
2 files changed, 20 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/64793/2

To view, visit change 64793. To unsubscribe, or for help writing mail filters, visit settings.