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Patch Set #2, Line 14: properly and no errors in boot log.
So before there were problems? Please cite one of these errors, so users with such an error may sear […]
any errors that might have occurred were early on when this board was initially ported without schematics, and the proper PCIe SRCCLK was not known, hence the trial and error in the original comment. The test comment here only serves to indicate that there were no issues with the change, enabling SRCCLK usage for the NVMe drive
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I159cb7ce1f5195d95c0229490c3bbde26edbd375
Gerrit-Change-Number: 40950
Gerrit-PatchSet: 2
Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Nico Huber <nico.h@gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-Comment-Date: Mon, 04 May 2020 15:15:10 +0000
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Comment-In-Reply-To: Paul Menzel <paulepanter@users.sourceforge.net>
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