Attention is currently required from: Patrick Rudolph.

Kyösti Mälkki has uploaded this change for review.

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[WIP] ACPI: Unify acpi_wake_source and CBMEM_ID_POWER_STATE

Change-Id: Ia6688ec7abf16ed15f3db5da41b6e5ed73ffbc7d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
M src/soc/intel/baytrail/ramstage.c
M src/soc/intel/broadwell/ramstage.c
2 files changed, 0 insertions(+), 96 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/49357/1

diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index f2c9cdc..ffb9675 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -2,7 +2,6 @@
 
 #include <arch/cpu.h>
 #include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/intel/microcode.h>
@@ -16,7 +15,6 @@
 #include <soc/gpio.h>
 #include <soc/lpc.h>
 #include <soc/msr.h>
-#include <soc/nvs.h>
 #include <soc/pattrs.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -116,33 +114,6 @@
 	attrs->bclk_khz = bus_freq_khz();
 }
 
-/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
-static void s3_save_acpi_wake_source(void)
-{
-	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
-	struct global_nvs *gnvs = acpi_get_gnvs();
-	uint16_t pm1;
-
-	if (!ps || !gnvs)
-		return;
-
-	pm1 = ps->pm1_sts & ps->pm1_en;
-
-	/* Scan for first set bit in PM1 */
-	for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
-		if (pm1 & 1)
-			break;
-		pm1 >>= 1;
-	}
-
-	/* If unable to determine then return -1 */
-	if (gnvs->pm1i >= 16)
-		gnvs->pm1i = -1;
-
-	printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n",
-	       gnvs->pm1i);
-}
-
 static void baytrail_enable_2x_refresh_rate(void)
 {
 	u32 reg;
@@ -164,10 +135,6 @@
 	/* Allow for SSE instructions to be executed. */
 	write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
 
-	/* Indicate S3 resume to rest of ramstage. */
-	if (acpi_is_wakeup_s3())
-		s3_save_acpi_wake_source();
-
 	/* Run reference code. */
 	baytrail_run_reference_code();
 
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index 2e50555..915bfd5 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -1,72 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <string.h>
-#include <soc/nvs.h>
-#include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/intel/broadwell/chip.h>
 
-/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
-static void save_acpi_wake_source(void)
-{
-	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
-	struct global_nvs *gnvs = acpi_get_gnvs();
-	uint16_t pm1;
-	int gpe_reg;
-
-	if (!ps || !gnvs)
-		return;
-
-	pm1 = ps->pm1_sts & ps->pm1_en;
-
-	/* Scan for first set bit in PM1 */
-	for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
-		if (pm1 & 1)
-			break;
-		pm1 >>= 1;
-	}
-
-	/* If unable to determine then return -1 */
-	if (gnvs->pm1i >= 16)
-		gnvs->pm1i = -1;
-
-	/* Scan for first set bit in GPE registers */
-	gnvs->gpei = -1;
-	for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) {
-		u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg];
-		int start = gpe_reg * GPE0_REG_SIZE;
-		int end = start + GPE0_REG_SIZE;
-
-		if (gpe == 0) {
-			if (!gnvs->gpei)
-				gnvs->gpei = end;
-			continue;
-		}
-
-		for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
-			if (gpe & 1)
-				break;
-			gpe >>= 1;
-		}
-	}
-
-	/* If unable to determine then return -1 */
-	if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE))
-		gnvs->gpei = -1;
-
-	printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
-	       gnvs->pm1i, gnvs->gpei);
-}
-
 void broadwell_init_pre_device(void *chip_info)
 {
-	if (acpi_is_wakeup_s3())
-		save_acpi_wake_source();
-
 	broadwell_run_reference_code();
 }

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