Martin Roth (martinroth@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12643
-gerrit
commit 5a3b3bfb895ec99ade6b4f0ec48eda595b8e26cc Author: Martin Roth martinroth@google.com Date: Fri Dec 4 08:33:35 2015 -0700
MAINTAINERS: Designate Intel maintainers for FSP 1.0 Rangeley
After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot.
They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal.
Change-Id: I7af7b37a5e3a233cc29adb20dd5bb8fa07dbdd53 Signed-off-by: Martin Roth martinroth@google.com --- MAINTAINERS | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS index 8c0f7a0..e811896 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -160,6 +160,21 @@ F: src/vendorcode/intel/fsp1_0/baytrail/ F: src/mainboard/intel/bakersport_fsp/ F: src/mainboard/intel/bayleybay_fsp/
+FSP 1.0 RANGELEY & CRB +M: David Guckian david.guckian@intel.com +M: Fei Wang fei.z.wang@intel.com +S: Supported +F: src/cpu/intel/fsp_model_406dx/ +F: src/northbridge/intel/fsp_rangeley/ +F: src/southbridge/intel/fsp_rangeley/ +F: src/vendorcode/intel/fsp1_0/rangeley/ +F: src/mainboard/intel/mohonpeak/ + +INTEL LITTLE PLAINS MAINBOARD +M: Marcin Wojciechowski marcin.wojciechowski@intel.com +S: Supported +F: src/mainboard/intel/littleplains/ + INTEL FSP 1.0 M: Huang Jin huang.jin@intel.com M: York Yang york.yang@intel.com