Kevin Chiu has uploaded this change for review.
mb/google/zork: update USB 3 controller phy Parameter for dirinboz
Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.
BUG=b:175192931
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run U3 SI/ESD pin test => pass
Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
---
M src/mainboard/google/zork/variants/dirinboz/overridetree.cb
1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/50282/1
diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
index 554cdea..626d281 100644
--- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
@@ -60,6 +60,26 @@
.tx_res_tune = 0x01,
}"
+ # USB3 phy parameter
+ register "usb3_phy_en" = "1"
+ # USB3 Port0 Default
+ register "usb3_phy_tune_params[0]" = "{
+ .rx_eq_delta_iq_ovrd_val = 0x8,
+ .rx_eq_delta_iq_ovrd_en = 0x1,
+ }"
+
+ # SUP_DIG_LVL_OVRD_IN Default
+ register "usb3_rx_vref_ctrl" = "0x10"
+ register "usb3_rx_vref_ctrl_en" = "0x00"
+ register "usb_3_tx_vboost_lvl" = "0x07"
+ register "usb_3_tx_vboost_lvl_en" = "0x01"
+
+ # SUPX_DIG_LVL_OVRD_IN Default
+ register "usb_3_rx_vref_ctrl_x" = "0x10"
+ register "usb_3_rx_vref_ctrl_en_x" = "0x00"
+ register "usb_3_tx_vboost_lvl_x" = "0x07"
+ register "usb_3_tx_vboost_lvl_en_x" = "0x01"
+
# I2C2 for touchscreen and trackpad
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
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