Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai.
View Change
1 comment:
Commit Message:
Patch Set #41, Line 9:
Refactor PCIE port config structure. Make it easier to map from schematic.
We don't have to convert the PCIE ports RP number and CLK source in devicetree.
All the convert will be done by SoC level.
reflow to 72 chars wide
Done
To view, visit change 48340. To unsubscribe, or for help writing mail filters, visit settings.
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Gerrit-Change-Number: 48340
Gerrit-PatchSet: 42
Gerrit-Owner: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath@intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Felix Singer <felixsinger@posteo.net>
Gerrit-CC: Angel Pons <th3fanbus@gmail.com>
Gerrit-CC: Michael Niewöhner <foss@mniewoehner.de>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-Attention: Furquan Shaikh <furquan@google.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Attention: Subrata Banik <subrata.banik@intel.com>
Gerrit-Attention: Angel Pons <th3fanbus@gmail.com>
Gerrit-Attention: Michael Niewöhner <foss@mniewoehner.de>
Gerrit-Attention: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Gerrit-Comment-Date: Wed, 13 Jan 2021 18:06:12 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-MessageType: comment