Nick Vaccaro has uploaded this change for review.

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mb/google/volteer: remove PCIe WWAN support

Remove support for PCIe WWAN to allow WWAN to enumerate as USB.

BUG=b:146226689
TEST=none

Change-Id: Ic71e88f7919757f6544a21b1df2e6d9a5a9ea8cc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
1 file changed, 2 insertions(+), 29 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/39354/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index ab50458..f2196df 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -50,7 +50,6 @@
register "PcieRpEnable[7]" = "1"
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
- register "sdcard_cd_gpio" = "GPP_E11"

# Enable WLAN PCIE 7 using clk 1
register "PcieRpEnable[6]" = "1"
@@ -107,23 +106,6 @@
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"

- # HD Audio
- register "PchHdaDspEnable" = "1"
- register "PchHdaAudioLinkHdaEnable" = "0"
- register "PchHdaAudioLinkDmicEnable[0]" = "1"
- register "PchHdaAudioLinkDmicEnable[1]" = "1"
- register "PchHdaAudioLinkSspEnable[0]" = "1"
- register "PchHdaAudioLinkSspEnable[1]" = "1"
- # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
- register "PchHdaIDispLinkTmode" = "2"
- # iDisp-Link Freq 4: 96MHz, 3: 48MHz.
- register "PchHdaIDispLinkFrequency" = "4"
- # Not disconnected/enumerable
- register "PchHdaIDispCodecDisconnect" = "0"
-
- # TCSS USB3
- register "TcssXhciEn" = "1"
-
# DP port
register "DdiPortAConfig" = "1" # eDP
register "DdiPortBConfig" = "0"
@@ -167,7 +149,7 @@
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
- #| GSPI1 | Fingerprint MCU |
+ #| GSPI1 | Fingerprint MCU
#| I2C0 | Audio |
#| I2C1 | Touchscreen |
#| I2C2 | WLAN, SAR0 |
@@ -340,16 +322,7 @@
device spi 0 on end
end
end # GSPI0 0xA0AA
- device pci 1e.3 on
- chip drivers/spi/acpi
- register "name" = ""CRFP""
- register "hid" = "ACPI_DT_NAMESPACE_HID"
- register "uid" = "1"
- register "compat_string" = ""google,cros-ec-spi""
- register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)"
- device spi 0 on end
- end # FPMCU
- end # GSPI1 0xA0AB
+ device pci 1e.3 on end # GSPI1 0xA0AB

device pci 1f.0 on end # eSPI 0xA080 - A09F
device pci 1f.1 off end # P2SB 0xA0A0

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic71e88f7919757f6544a21b1df2e6d9a5a9ea8cc
Gerrit-Change-Number: 39354
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com>
Gerrit-MessageType: newchange