Attention is currently required from: Gaggery Tsai, Marx Wang.

Marx Wang uploaded patch set #15 to this change.

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soc/intel/apollolake: Provide the option to enable DDR 2x refresh rate

We need to enable 2x refresh rate in order to mitigate Row Hammer
vulnerability for the boards with specific DRAMs. To enable it, we
can add "enable_row_hammer_mitigation" attribute in board's lpddr4
memory config.
for example:

static const struct lpddr4_sku cbi_skus[] = {
        /* Dual Channel Config 4GiB System Capacity */
        .............
        ................................
        /* Dual Channel Config 8GiB System Capacity */
        [1] = {
                .speed = LP4_SPEED_2400,
                .ch0_rank_density = LP4_16Gb_DENSITY,
                .ch1_rank_density = LP4_16Gb_DENSITY,
                .enable_row_hammer_mitigation = 1,
        },

BUG=b:152151369
TEST=add "enable_row_hammer_mitigation" attribute for specific DRAMs,
build the image and run "suspend_stress_test" with memory check for
2500 cycles.

Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: I0235fc7906626f28f14367c283433e5b066cc89a
---
M src/soc/intel/apollolake/include/soc/meminit.h
M src/soc/intel/apollolake/meminit.c
2 files changed, 10 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/48510/15

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