Benjamin Doron uploaded patch set #27 to this change.
soc/intel/skylake: Configure L1 substates for PCH root ports
Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration.
Tested on an Acer Aspire VN7-572G (Skylake-U).
Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/27
To view, visit change 39538. To unsubscribe, or for help writing mail filters, visit settings.