Patrick Georgi (patrick@georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4460
-gerrit
commit 7b16fdffb3675095b257b816362ed03307fb4e4d Author: David Hendricks dhendrix@chromium.org Date: Thu Aug 8 16:04:07 2013 -0700
exynos5420: correct the PMS value for CPLL
This patch matches the User Manual Table 7-2 about the PMS value for CPLL. This doesn't change the PLL frequency (before and after both make 666MHz) but this is the suggested PMSK values for obtaining 666. (Suggested as per user manual).
This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/
Signed-off-by: David Hendricks dhendrix@chromium.org
Change-Id: Ia33e1971ab88da761000d443792560476514626b Reviewed-on: https://gerrit.chromium.org/gerrit/65281 Reviewed-by: Gabe Black gabeblack@chromium.org Commit-Queue: David Hendricks dhendrix@chromium.org Tested-by: David Hendricks dhendrix@chromium.org --- src/cpu/samsung/exynos5420/clock_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 3521636..07bf5d9 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -113,7 +113,7 @@ void system_clock_init(void)
/* Set CPLL */ writel(CPLL_CON1_VAL, &clk->cpll_con1); - val = set_pll(0x6f, 0x2, 0x1); + val = set_pll(0xde, 0x4, 0x1); writel(val, &clk->cpll_con0); while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0) ;