John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41386 )
Change subject: Enable TCSS DMA0 and DMA1 for TGL RVP platform ......................................................................
Enable TCSS DMA0 and DMA1 for TGL RVP platform
This explicitly enables both of TCSS DMA0 and DMA1 controllers from TGL RVP platform devicetree setting.
BUG=:b:146624360 TEST=Built and booted on TGL RVP.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 16 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/41386/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 82f358e..8992722 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -110,8 +110,14 @@ }"
# TCSS USB3 + register "TcssXhciEn" = "1" + register "TcssXdciEn" = "0" register "TcssAuxOri" = "0"
+ # TCSS DMA + register "TcssDma0En" = "1" + register "TcssDma1En" = "1" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -158,8 +164,8 @@ device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 off end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0d.2 on end # TBT DMA0 0x9A1B + device pci 0d.3 on end # TBT DMA1 0x9A1D device pci 0e.0 on end # VMD 0x9A0B
# From PCH EDS(576591) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fec2fef..6839965 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -106,8 +106,14 @@ }"
# TCSS USB3 + register "TcssXhciEn" = "1" + register "TcssXdciEn" = "0" register "TcssAuxOri" = "0"
+ # TCSS DMA + register "TcssDma0En" = "1" + register "TcssDma1En" = "1" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -154,8 +160,8 @@ device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 off end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0d.2 on end # TBT DMA0 0x9A1B + device pci 0d.3 on end # TBT DMA1 0x9A1D device pci 0e.0 on end # VMD 0x9A0B
# From PCH EDS(576591)