[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/cse: Implement APIs to access PSR backup status in CMOS

[Anil Kumar K (Code Review)]

Attention is currently required from: Jérémy Compostella, Krishna P Bhat D, Rizwan Qureshi, Subrata Banik, sridhar siricilla.

Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77069?usp=email )

Change subject: soc/intel/cse: Implement APIs to access PSR backup status in CMOS
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Patch Set 8:

(4 comments)

File src/soc/intel/common/block/cse/cse_lite_cmos.c:

https://review.coreboot.org/c/coreboot/+/77069/comment/b929552c_4c713e6f :
PS7, Line 113: int8_t
> int ?

kept it int8_t as value is either 1 or 0

File src/soc/intel/common/block/include/intelblocks/cse.h:

https://review.coreboot.org/c/coreboot/+/77069/comment/b6e900ba_2b829ed4 :
PS7, Line 176: backup_status
> nit: status or value […]

Acknowledged

https://review.coreboot.org/c/coreboot/+/77069/comment/b06ef769_c704bd5d :
PS7, Line 176: int8_t
> int

int8_t as the value if either 0 or 1

File src/soc/intel/common/block/include/intelblocks/cse.h:

https://review.coreboot.org/c/coreboot/+/77069/comment/a2c1ac65_8231004a :
PS5, Line 171: 0x55
> > Hi Subrata , We kept the values 0x55 and 0x22 to make sure these are not commonly occuring values  […]

Acknowledged