Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21856
Change subject: soc/amd/common: Add DRAM clear option to agesawrapper ......................................................................
soc/amd/common: Add DRAM clear option to agesawrapper
AmdInitPost() can be instructed to clear DRAM after a reset or to preserve it. Expand agesawrapper.c to tell AGESA which action to take.
Note that any overrides in place are not affected by this change.
Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/common/agesawrapper.c M src/soc/amd/stoneyridge/chip.h 2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/21856/1
diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index 659797a..93f7eb4 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -142,6 +142,8 @@ PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
if (cfg) { + PostParams->MemConfig.EnableMemClr = cfg->dram_clear; + PostParams->MemConfig.UmaMode = cfg->uma_mode; PostParams->MemConfig.UmaVersion = cfg->uma_type; if (cfg->uma_mode == UMAMODE_SPECIFIED) diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 01127b0..f73b252 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -49,6 +49,12 @@ u32 uma_size;
u8 spdAddrLookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; + u8 dram_clear; + /* Clear DRAM - must correspond to AGESA TRUE */ + #define DRAM_CONTENTS_CLEAR 1 + /* Do not clear DRAM - must correspond to AGESA FALSE */ + #define DRAM_CONTENTS_KEEP 0 + u32 ide0_enable : 1; u32 sata0_enable : 1; u32 boot_switch_sata_ide : 1;