Felix Held has uploaded this change for review.
soc/amd/cezanne: add common SMBus code to build
Since the IOAPIC in the FCH gets set up in the SMBus code, also select
IOAPIC in Kconfig.
Change-Id: I4163e28ca9e68e5fd36421d90aafc20bce43a174
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
---
M src/soc/amd/cezanne/Kconfig
A src/soc/amd/cezanne/include/soc/iomap.h
A src/soc/amd/cezanne/include/soc/southbridge.h
3 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/48474/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 2a26d6d..aec9a47 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -13,11 +13,13 @@
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
+ select IOAPIC
select RESET_VECTOR_IN_RAM
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+ select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
config EARLY_RESERVED_DRAM_BASE
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
new file mode 100644
index 0000000..7f1b77d
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_PICASSO_IOMAP_H
+#define AMD_PICASSO_IOMAP_H
+
+/* I/O Ranges */
+#define SMB_BASE_ADDR 0xb00
+
+#endif /* AMD_PICASSO_IOMAP_H */
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
new file mode 100644
index 0000000..0f26ff0
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_SOUTHBRIDGE_H
+#define AMD_CEZANNE_SOUTHBRIDGE_H
+
+#include <soc/iomap.h>
+
+#endif /* AMD_CEZANNE_SOUTHBRIDGE_H */
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