Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49407 )
Change subject: soc/intel/common/gpio: Add gpio_routes_ioapic_irq function ......................................................................
soc/intel/common/gpio: Add gpio_routes_ioapic_irq function
This function returns true if any GPIO pad is programmed to route the given IRQ to the IO-APIC. It does so by keeping track of which pads are routed to IOxAPIC and looking this up in the new function.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h 2 files changed, 30 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 28e78fb..fcce8d7 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -210,6 +210,24 @@ pcr_or32(comm->port, en_reg, en_value); }
+/* 120 GSIs is the default for IOxAPIC */ +static uint32_t gpio_ioapic_irqs_used[120 / (sizeof(uint32_t) * BITS_PER_BYTE) + 1]; +static void set_ioapic_used(uint32_t irq) +{ + size_t word_offset = irq / 32; + size_t bit_offset = irq % 32; + assert (word_offset < ARRAY_SIZE(gpio_ioapic_irqs_used)); + gpio_ioapic_irqs_used[word_offset] |= BIT(bit_offset); +} + +bool gpio_routes_ioapic_irq(uint32_t irq) +{ + size_t word_offset = irq / 32; + size_t bit_offset = irq % 32; + assert (word_offset < ARRAY_SIZE(gpio_ioapic_irqs_used)); + return (gpio_ioapic_irqs_used[word_offset] & BIT(bit_offset)) != 0; +} + static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, uint16_t pad_cfg_offset) { @@ -217,9 +235,6 @@ if (ENV_SMM) return;
- if (!CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) - return; - int irq;
/* Set up ITSS polarity if pad is routed to APIC. @@ -242,8 +257,12 @@ cfg->pad); return; } - itss_set_irq_polarity(irq, !!(cfg->pad_config[0] & - PAD_CFG0_RX_POL_INVERT)); + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) + itss_set_irq_polarity(irq, !!(cfg->pad_config[0] & + PAD_CFG0_RX_POL_INVERT)); + + set_ioapic_used(irq); }
/* Number of DWx config registers can be different for different SOCs */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 4c29a0c..45ae1da 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -229,5 +229,11 @@ */ void block_gpio_enable(struct device *dev);
+/* + * Returns true if any GPIO that uses the specified IRQ is also programmed to + * route IRQs to IOAPIC. + */ +bool gpio_routes_ioapic_irq(unsigned int irq); + #endif #endif /* _SOC_INTELBLOCKS_GPIO_H_ */