Patrick Georgi submitted this change.
soc/amd/common: add Kconfig help text to pre-family-17h-only blocks
The cpu/car code only applies to pre-family-17h CPUs that still use
cache as RAM (CAR) and the PI code only applies to the pre-FSP vendor
code blob binaryPI interface.
Change-Id: I5a13d7e202bb745255fabb46110850c36b07de7a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47274
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/amd/common/block/cpu/Kconfig
M src/soc/amd/common/block/pi/Kconfig
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index 5941599..f6756e1 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -8,3 +8,6 @@
it may not be appropriate for a romstage implementation without
additional consideration. If this option is not used, the SOC must
implement these functions separately.
+ This is only used for AMD CPU before family 17h. From family 17h on
+ the RAM is already initialized by the PSP before the x86 cores are
+ released from reset.
diff --git a/src/soc/amd/common/block/pi/Kconfig b/src/soc/amd/common/block/pi/Kconfig
index f0917bb..cf8c79a 100644
--- a/src/soc/amd/common/block/pi/Kconfig
+++ b/src/soc/amd/common/block/pi/Kconfig
@@ -3,7 +3,8 @@
select HAVE_DEBUG_RAM_SETUP
default n
help
- This option builds functions that interface AMD's AGESA.
+ This option builds functions that interface AMD's AGESA reference
+ code packaged in the binaryPI form.
if SOC_AMD_COMMON_BLOCK_PI
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