Arthur Heymans has uploaded this change for review.
cpu/x86: Select proper SMM save Kconfig option
Note: Qemu always uses AMD64 save states but messes up the revision if
the CPU is set to be a 32bit-only one the save state revision is 0 but
still uses the AMD64 one. This is currently not handled by coreboot.
Change-Id: If045a04b6617eefc79a117486a9b224f4ca96b17
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/cpu/amd/agesa/Kconfig
M src/cpu/amd/pi/Kconfig
M src/cpu/intel/haswell/Kconfig
M src/cpu/intel/model_1067x/Kconfig
M src/cpu/intel/model_106cx/Kconfig
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/intel/model_206ax/Kconfig
M src/cpu/intel/model_f2x/Kconfig
M src/cpu/intel/model_f3x/Kconfig
M src/cpu/intel/model_f4x/Kconfig
M src/cpu/intel/slot_1/Kconfig
M src/cpu/intel/socket_441/Kconfig
M src/cpu/intel/socket_BGA956/Kconfig
M src/cpu/intel/socket_LGA775/Kconfig
M src/cpu/intel/socket_m/Kconfig
M src/cpu/intel/socket_mPGA604/Kconfig
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-q35/Kconfig
M src/soc/amd/picasso/Kconfig
M src/soc/amd/stoneyridge/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/braswell/Kconfig
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/skylake/Kconfig
M src/soc/intel/tigerlake/Kconfig
30 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45473/1
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 499cc5b..538fb6c 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -18,6 +18,7 @@
select SMM_ASEG
select SSE2
select ACPI_NO_SMI_GNVS
+ select X86_AMD64_SAVE_STATE
if CPU_AMD_AGESA
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index 533507e..0aa3183 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -18,6 +18,7 @@
select SMM_ASEG
select SSE2
select ACPI_NO_SMI_GNVS
+ select X86_AMD64_SAVE_STATE
if CPU_AMD_PI
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 18fc392..1242dd7 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -21,6 +21,7 @@
select PARALLEL_MP
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
+ select X86_EM64T101_SAVE_STATE
config SMM_TSEG_SIZE
hex
diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
index 0a29d69..b29d426 100644
--- a/src/cpu/intel/model_1067x/Kconfig
+++ b/src/cpu/intel/model_1067x/Kconfig
@@ -12,3 +12,4 @@
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select SETUP_XIP_CACHE
+ select X86_EM64T101_SAVE_STATE
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index 095fee5..44d9805 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -14,6 +14,8 @@
select SERIALIZED_SMM_INITIALIZATION
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
+ select X86_LEGACY_SAVE_STATE
+ select X86_EM64T101_SAVE_STATE
if CPU_INTEL_MODEL_106CX
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index 78cac30..de3e835 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -19,6 +19,7 @@
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select PARALLEL_MP
+ select X86_EM64T101_SAVE_STATE
config SMM_TSEG_SIZE
hex
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 1918428..abb8eba 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -19,6 +19,7 @@
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select PARALLEL_MP
+ select X86_EM64T101_SAVE_STATE
config SMM_TSEG_SIZE
hex
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
index 0c92479..50c64b9 100644
--- a/src/cpu/intel/model_f2x/Kconfig
+++ b/src/cpu/intel/model_f2x/Kconfig
@@ -8,3 +8,5 @@
select SMM_ASEG
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_HYPERTHREADING
+ select X86_LEGACY_SAVE_STATE
+ select X86_EM64T101_SAVE_STATE
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig
index fbb00fa..60eeac7 100644
--- a/src/cpu/intel/model_f3x/Kconfig
+++ b/src/cpu/intel/model_f3x/Kconfig
@@ -7,3 +7,5 @@
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_HYPERTHREADING
+ select X86_LEGACY_SAVE_STATE
+ select X86_EM64T101_SAVE_STATE
diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig
index 9398d18..91adff9 100644
--- a/src/cpu/intel/model_f4x/Kconfig
+++ b/src/cpu/intel/model_f4x/Kconfig
@@ -5,3 +5,4 @@
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS
+ select X86_EM64T101_SAVE_STATE
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 2b6deb6..720ce11 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -17,6 +17,7 @@
select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE
select SETUP_XIP_CACHE
+ select X86_LEGACY_SAVE_STATE
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index af43f72..9c5f292 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -9,6 +9,7 @@
select MMX
select SSE
select SETUP_XIP_CACHE
+ select X86_EM64T101_SAVE_STATE
config C_ENV_BOOTBLOCK_SIZE
hex
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig
index 638653c..b903fdf 100644
--- a/src/cpu/intel/socket_BGA956/Kconfig
+++ b/src/cpu/intel/socket_BGA956/Kconfig
@@ -3,6 +3,7 @@
select CPU_INTEL_MODEL_1067X
select MMX
select SSE
+ select X86_EM64T101_SAVE_STATE
if CPU_INTEL_SOCKET_BGA956
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8db932c..2c2141c 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -14,6 +14,7 @@
select MMX
select SSE
select SIPI_VECTOR_IN_ROM
+ select X86_EM64T101_SAVE_STATE
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig
index 8b1f5ed..0ca7c99 100644
--- a/src/cpu/intel/socket_m/Kconfig
+++ b/src/cpu/intel/socket_m/Kconfig
@@ -9,6 +9,8 @@
select CPU_INTEL_MODEL_6FX
select MMX
select SSE
+ select X86_LEGACY_SAVE_STATE
+ select X86_EM64T101_SAVE_STATE
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index 176ae9e..8911a8d 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -13,6 +13,7 @@
select SIPI_VECTOR_IN_ROM
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
+ select X86_EM64T101_SAVE_STATE
# mPGA604 are usually Intel Netburst CPUs which should have SSE2
# but the ramtest.c code on the Dell S1850 seems to choke on
diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig
index 06ac685..6aa081b 100644
--- a/src/mainboard/emulation/qemu-i440fx/Kconfig
+++ b/src/mainboard/emulation/qemu-i440fx/Kconfig
@@ -13,6 +13,7 @@
select BOARD_ROMSIZE_KB_16384 if VBOOT
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_FORCE_NATIVE_VGA_INIT
+ select X86_AMD64_SAVE_STATE
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index edd2b2c..19fb1d3 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -15,6 +15,7 @@
select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_CHROMEOS
+ select X86_AMD64_SAVE_STATE
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 526900a..7e28e27 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -58,6 +58,7 @@
select HAVE_CF9_RESET
select SUPPORT_CPU_UCODE_IN_CBFS
select ACPI_NO_SMI_GNVS
+ select X86_AMD64_SAVE_STATE
config MEMLAYOUT_LD_FILE
string
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index b29bd99..59f6a66 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -48,6 +48,7 @@
select SSE2
select RTC
select ACPI_NO_SMI_GNVS
+ select X86_AMD64_SAVE_STATE
config AMD_APU_STONEYRIDGE
bool
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index f837a2e..817c3e8 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -105,6 +105,7 @@
select NO_UART_ON_SUPERIO
select INTEL_GMA_ACPI
select INTEL_GMA_SWSMISCI
+ select X86_EM64T100_SAVE_STATE
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index b23f56d..a74f243 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -37,6 +37,7 @@
select INTEL_GMA_SWSMISCI
select CPU_INTEL_COMMON
select CPU_HAS_L2_ENABLE_MSR
+ select X86_EM64T100_SAVE_STATE
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index bf067da..2e7d32e 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -44,6 +44,7 @@
select CPU_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
+ select X86_EM64T100_SAVE_STATE
config DCACHE_BSP_STACK_SIZE
hex
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 156d58a..7b0a0bd 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -43,6 +43,7 @@
select INTEL_GMA_ACPI
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+ select X86_EM64T101_SAVE_STATE
config PCIEXP_ASPM
bool
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index d36e214..981ac69 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -113,6 +113,7 @@
select DISPLAY_FSP_VERSION_INFO
select FSP_T_XIP if FSP_CAR
select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
+ select X86_EM64T101_SAVE_STATE
config MAX_CPUS
int
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 3fce223..202704a8 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -40,6 +40,7 @@
select UDK_2015_BINDING
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select SUPPORT_CPU_UCODE_IN_CBFS
+ select X86_EM64T100_SAVE_STATE
config MMCONF_BASE_ADDRESS
hex
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 1230675..bc4c44c 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -61,6 +61,7 @@
select DISPLAY_FSP_VERSION_INFO
select HECI_DISABLE_USING_SMM
select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
+ select X86_EM64T101_SAVE_STATE
config DCACHE_RAM_BASE
default 0xfef00000
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index f2922f5..2f23c5f 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -62,6 +62,7 @@
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
select HECI_DISABLE_USING_SMM
+ select X86_EM64T101_SAVE_STATE
config DCACHE_RAM_BASE
default 0xfef00000
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 9f9cb18..338a5be 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -79,6 +79,7 @@
select TSC_SYNC_MFENCE
select UDELAY_TSC
select UDK_2015_BINDING
+ select X86_EM64T101_SAVE_STATE
config FSP_HYPERTHREADING
bool "Enable Hyper-Threading"
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 2659357..beb87ca 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -62,6 +62,7 @@
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
select HECI_DISABLE_USING_SMM
+ select X86_EM64T101_SAVE_STATE
config DCACHE_RAM_BASE
default 0xfef00000
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